Introduction to CMOS VLSI Design Circuit Families 1
- Slides: 34
Introduction to CMOS VLSI Design Circuit Families 1
Outline q Pseudo-n. MOS Logic q Dynamic Logic q Pass Transistor Logic Circuit Families CMOS VLSI Design 2
Introduction q What makes a circuit fast? – I = C d. V/dt -> tpd (C/I) DV – low capacitance – high current – small swing q Logical effort is proportional to C/I q p. MOS are the enemy! – High capacitance for a given current q Can we take the p. MOS capacitance off the input? q Various circuit families try to do this… Circuit Families CMOS VLSI Design 3
Pseudo-n. MOS q In the old days, n. MOS processes had no p. MOS – Instead, use pull-up transistor that is always ON q In CMOS, use a p. MOS that is always ON – Ratio issue – Make p. MOS about ¼ effective strength of pulldown network Circuit Families CMOS VLSI Design 4
Pseudo-n. MOS Gates q Design for unit current on output to compare with unit inverter. q p. MOS fights n. MOS Circuit Families CMOS VLSI Design 5
Pseudo-n. MOS Gates q Design for unit current on output to compare with unit inverter. q p. MOS fights n. MOS Circuit Families CMOS VLSI Design 6
Pseudo-n. MOS Gates q Design for unit current on output to compare with unit inverter. q p. MOS fights n. MOS Circuit Families CMOS VLSI Design 7
Pseudo-n. MOS Gates q Design for unit current on output to compare with unit inverter. q p. MOS fights n. MOS Circuit Families CMOS VLSI Design 8
Pseudo-n. MOS Design q Ex: Design a k-input AND gate using pseudo-n. MOS. Estimate the delay driving a fanout of H q q q G= F= P= N= D= Circuit Families CMOS VLSI Design 9
Pseudo-n. MOS Design q Ex: Design a k-input AND gate using pseudo-n. MOS. Estimate the delay driving a fanout of H q q q G = 1 * 8/9 = 8/9 F = GBH = 8 H/9 P = 1 + (4+8 k)/9 = (8 k+13)/9 N=2 D = NF 1/N + P = Circuit Families CMOS VLSI Design 10
Pseudo-n. MOS Power q Pseudo-n. MOS draws power whenever Y = 0 – Called static power P = I • VDD – A few m. A / gate * 1 M gates would be a problem – This is why n. MOS went extinct! q Use pseudo-n. MOS sparingly for wide NORs q Turn off p. MOS when not in use Circuit Families CMOS VLSI Design 11
Dynamic Logic q Dynamic gates uses a clocked p. MOS pullup q Two modes: precharge and evaluate Circuit Families CMOS VLSI Design 12
The Foot q What if pulldown network is ON during precharge? q Use series evaluation transistor to prevent fight. Circuit Families CMOS VLSI Design 13
Logical Effort Circuit Families CMOS VLSI Design 14
Logical Effort Circuit Families CMOS VLSI Design 15
Monotonicity q Dynamic gates require monotonically rising inputs during evaluation – 0 -> 0 – 0 -> 1 – 1 -> 1 – But not 1 -> 0 Circuit Families CMOS VLSI Design 16
Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another! Circuit Families CMOS VLSI Design 17
Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another! Circuit Families CMOS VLSI Design 18
Domino Gates q Follow dynamic stage with inverting static gate – Dynamic / static pair is called domino gate – Produces monotonic outputs Circuit Families CMOS VLSI Design 19
Domino Optimizations q Each domino gate triggers next one, like a string of dominos toppling over q Gates evaluate sequentially but precharge in parallel q Thus evaluation is more critical than precharge q HI-skewed static stages can perform logic Circuit Families CMOS VLSI Design 20
Dual-Rail Domino q Domino only performs noninverting functions: – AND, OR but not NAND, NOR, or XOR q Dual-rail domino solves this problem – Takes true and complementary inputs – Produces true and complementary outputs sig_h sig_l Meaning 0 0 Precharged 0 1 ‘ 0’ 1 0 ‘ 1’ 1 1 invalid Circuit Families CMOS VLSI Design 21
Example: AND/NAND q Given A_h, A_l, B_h, B_l q Compute Y_h = A * B, Y_l = ~(A * B) Circuit Families CMOS VLSI Design 22
Example: AND/NAND q Given A_h, A_l, B_h, B_l q Compute Y_h = A * B, Y_l = ~(A * B) q Pulldown networks are conduction complements Circuit Families CMOS VLSI Design 23
Example: XOR/XNOR q Sometimes possible to share transistors Circuit Families CMOS VLSI Design 24
Leakage q Dynamic node floats high during evaluation – Transistors are leaky (IOFF 0) – Dynamic value will leak away over time – Formerly miliseconds, now nanoseconds! q Use keeper to hold dynamic node – Must be weak enough not to fight evaluation Circuit Families CMOS VLSI Design 25
Charge Sharing q Dynamic gates suffer from charge sharing Circuit Families CMOS VLSI Design 26
Charge Sharing q Dynamic gates suffer from charge sharing Circuit Families CMOS VLSI Design 27
Charge Sharing q Dynamic gates suffer from charge sharing Circuit Families CMOS VLSI Design 28
Secondary Precharge q Solution: add secondary precharge transistors – Typically need to precharge every other node q Big load capacitance CY helps as well Circuit Families CMOS VLSI Design 29
Noise Sensitivity q Dynamic gates are very sensitive to noise – Inputs: VIH Vtn – Outputs: floating output susceptible noise q Noise sources – Capacitive crosstalk – Charge sharing – Power supply noise – Feedthrough noise – And more! Circuit Families CMOS VLSI Design 30
Domino Summary q Domino logic is attractive for high-speed circuits – 1. 5 – 2 x faster than static CMOS – But many challenges: • Monotonicity • Leakage • Charge sharing • Noise q Widely used in high-performance microprocessors Circuit Families CMOS VLSI Design 31
Pass Transistor Circuits q Use pass transistors like switches to do logic q Inputs drive diffusion terminals as well as gates q CMOS + Transmission Gates: – 2 -input multiplexer – Gates should be restoring Circuit Families CMOS VLSI Design 32
LEAP q LEAn integration with Pass transistors q Get rid of p. MOS transistors – Use weak p. MOS feedback to pull fully high – Ratio constraint Circuit Families CMOS VLSI Design 33
CPL q Complementary Pass-transistor Logic – Dual-rail form of pass transistor logic – Avoids need for ratioed feedback – Optional cross-coupling for rail-to-rail swing Circuit Families CMOS VLSI Design 34
- Circuit families in vlsi
- Layout design rules in cmos vlsi
- Cmos vlsi design lecture notes
- Device modeling for analog and rf cmos circuit design
- Razavi cmos analog circuit design
- Cmos inverter layout
- What are the characteristics of logic families
- Little families
- Introduction to vlsi design
- Cmos inverter vtc
- Sr latch using cmos
- Latchup in vlsi
- Circuit pitfalls in vlsi
- Or logic gate
- Memory design in vlsi
- Y chart in vlsi design
- Biucache
- Subsystem design in vlsi notes
- Mixed signal vlsi design
- Rom design in vlsi
- Vlsi design tutorial
- Y chart in vlsi design
- Modularity in vlsi
- Ad hoc testable design techniques
- Structured vlsi design
- Vlsi physical design automation
- Vlsi design styles
- Stuck at fault
- Vlsi design flow
- 2:1 mux stick diagram
- åq
- Rom design in vlsi
- Parallel vs series
- Types of electrical circuits
- Circuit construction kit