Fundamentals of Digital Test and DFT Vishwani D

Fundamentals of Digital Test and DFT Vishwani D. Agrawal Rutgers University, Dept. of ECE New Jersey http: //cm. bell-labs. com/cm/cs/who/va January 2003 Agrawal: Digital Test and DFT 1

Course Outline § § § § 2003 Basic concepts and definitions Fault modeling Fault simulation ATPG DFT and scan design BIST Boundary scan IDDQ test Agrawal: Digital Test and DFT 2

VLSI Realization Process Customer’s need Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacturing test Chips to customer 2003 Agrawal: Digital Test and DFT 3

Definitions n n n Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect. 2003 Agrawal: Digital Test and DFT 4

Realities of Tests n n 2003 Based on analyzable fault models, which may not map onto real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level. Agrawal: Digital Test and DFT 5

Costs of Testing n Design for testability (DFT) § Chip area overhead and yield reduction § Performance overhead n n Software processes of test § Test generation and fault simulation § Test programming and debugging Manufacturing test § Automatic test equipment (ATE) capital cost § Test center operational cost 2003 Agrawal: Digital Test and DFT 6

Cost of Manufacturing Testing in 2000 AD n n n 2003 0. 5 -1. 0 GHz, analog instruments, 1, 024 digital pins: ATE purchase price § = $1. 2 M + 1, 024 x $3, 000 = $4. 272 M Running cost (five-year linear depreciation) § = Depreciation + Maintenance + Operation § = $0. 854 M + $0. 085 M + $0. 5 M § = $1. 439 M/year Test cost (24 hour ATE operation) § = $1. 439 M/(365 x 24 x 3, 600) § = 4. 5 cents/second Agrawal: Digital Test and DFT 7

Present and Future* 1997 --2001 2003 --2006 Feature size (micron) 0. 25 - 0. 15 0. 13 - 0. 10 Transistors/sq. cm Pin count Clock rate (MHz) Power (Watts) 18 - 39 M 160 - 1475 530 - 1100 2 - 96 4 - 10 M 100 - 900 200 - 730 1. 2 - 61 * SIA Roadmap, IEEE Spectrum, July 1999 2003 Agrawal: Digital Test and DFT 8

Method of Testing 2003 Agrawal: Digital Test and DFT 9

ADVANTEST Model T 6682 ATE 2003 Agrawal: Digital Test and DFT 10

LTX FUSION HF ATE 2003 Agrawal: Digital Test and DFT 11

VLSI Chip Yield n n A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. Cost of a chip: Cost of fabricating and testing a wafer ----------------------------------Yield x Number of chip sites on the wafer 2003 Agrawal: Digital Test and DFT 12

Defect Level or Reject Ratio n n 2003 Defect level (DL) is the ratio of faulty chips among the chips that pass tests. DL is measured as parts per million (ppm). DL is a measure of the effectiveness of tests. DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable. Agrawal: Digital Test and DFT 13

Example: SEMATECH Chip n n n n 2003 Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont 116, 000 equivalent (2 -input NAND) gates 304 -pin package, 249 I/O Clock: 40 MHz, some parts 50 MHz 0. 45 m CMOS, 3. 3 V, 9. 4 mm x 8. 8 mm area Full scan, 99. 79% fault coverage Advantest 3381 ATE, 18, 466 chips tested at 2. 5 MHz test clock Data obtained courtesy of Phil Nigh (IBM) Agrawal: Digital Test and DFT 14

Computed DL Defect level in ppm 237, 700 ppm (Y = 76. 23%) Stuck-at fault coverage (%) 2003 Agrawal: Digital Test and DFT 15

Summary: Introduction n n VLSI Yield drops as chip area increases; low yield means high cost Fault coverage measures the test quality Defect level (DL) or reject ratio is a measure of chip quality DL can be determined by an analysis of test data For high quality: DL < 500 ppm, fault coverage ~ 99% 2003 Agrawal: Digital Test and DFT 16

Fault Modeling 2003 Agrawal: Digital Test and DFT 17

Why Model Faults? n n n 2003 I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments Agrawal: Digital Test and DFT 18

Some Real Defects in Chips n n Processing defects n Missing contact windows n Parasitic transistors n Oxide breakdown n. . . Material defects n Bulk defects (cracks, crystal imperfections) n Surface impurities (ion migration) n. . . Time-dependent failures n Dielectric breakdown n Electromigration n. . . Packaging failures n Contact degradation n Seal leaks n. . . Ref. : M. J. Howes and D. V. Morgan, Reliability and Degradation Semiconductor Devices and Circuits, Wiley, 1981. 2003 Agrawal: Digital Test and DFT 19

Observed PCB Defects Occurrence frequency (%) Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) 51 1 6 13 6 8 5 5 5 Ref. : J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985. 2003 Agrawal: Digital Test and DFT 20

Common Fault Models n n n n 2003 Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults For more examples, see Section 4. 4 (p. 6070) of the book. Agrawal: Digital Test and DFT 21

Single Stuck-at Fault n Three properties define a single stuck-at fault n n Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults c 1 0 a d b e f Faulty circuit value Good circuit value j s-a-0 g 1 0(1) 1(0) h i k z 1 Test vector for h s-a-0 fault 2003 Agrawal: Digital Test and DFT 22

Fault Equivalence n n Number of fault sites in a Boolean gate circuit = #PI + #gates + #(fanout branches). Fault equivalence: Two faults f 1 and f 2 are equivalent if all tests that detect f 1 also detect f 2. If faults f 1 and f 2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuits can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset. 2003 Agrawal: Digital Test and DFT 23

Equivalence Example sa 0 sa 1 sa 0 sa 1 sa 0 sa 1 sa 0 sa 1 2003 sa 0 sa 1 Faults in red removed by equivalence collapsing 20 Collapse ratio = ----- = 0. 625 32 Agrawal: Digital Test and DFT 24

Summary: Fault Models n n n 2003 Fault models are analyzable approximations of defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck -at fault tests. Stuck-short and delay faults and technologydependent faults require special tests. Memory and analog circuits need other specialized fault models and tests. Agrawal: Digital Test and DFT 25

Fault Simulation 2003 Agrawal: Digital Test and DFT 26

Problem and Motivation n Fault simulation Problem: Given n § Determine n n n Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults Motivation n n 2003 A circuit A sequence of test vectors A fault model Determine test quality and in turn product quality Find undetected fault targets to improve tests Agrawal: Digital Test and DFT 27

Fault simulator in a VLSI Design Process Verified design netlist Verification input stimuli Fault simulator Test vectors Modeled Remove fault list tested faults Fault coverage ? Low Test Delete compactor vectors Test generator Add vectors Adequate Stop 2003 Agrawal: Digital Test and DFT 28

Fault Simulation Scenario n Circuit model: mixed-level n n n Signal states: logic n n n Mostly logic with some switch-level for highimpedance (Z) and bidirectional signals High-level models (memory, etc. ) with pin faults Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits Four states (0, 1, X, Z) for sequential MOS circuits Timing: n n 2003 Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback Agrawal: Digital Test and DFT 29

Fault Simulation Scenario (continued) n Faults: n n n 2003 Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck-at faults Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis Fault sampling -- a random sample of faults is simulated when the circuit is large Agrawal: Digital Test and DFT 30

Essence of Fault Sim. Test vectors Fault-free circuit Comparator f 1 detected? Comparator f 2 detected? Comparator fn detected? Circuit with fault f 1 Circuit with fault f 2 Circuit with fault fn n n Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits Alternative: Simulate many faults together 2003 Agrawal: Digital Test and DFT 31

Fault Sampling n n 2003 A randomly selected subset (sample) of faults is simulated. Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage: Saving in computing resources (CPU time and memory. ) Disadvantage: Limited data on undetected faults. Agrawal: Digital Test and DFT 32

Random Sampling Model Detected fault All faults with a fixed but unknown coverage Random picking Np = total number of faults Ns = sample size Ns << Np (population size) C = fault coverage (unknown) 2003 Undetected fault c = sample coverage Agrawal: Digital Test and DFT (a random variable) 33

Probability Density of Sample Coverage, c (x--C )2 -- ------ 1 p (x ) = Prob(x < c < x +dx ) = -------s (2 p) p (x ) C (1 - C) 2 Variance, s = ------Ns s C e 2 Sampling error s Mean = C C -3 s 1/2 2 s x C +3 s 1. 0 x Sample coverage 2003 Agrawal: Digital Test and DFT 34

Sampling Error Bounds |x-C|=3 C (1 - C ) 1/2 [ -------] N s Solving the quadratic equation for C, we get the 3 -sigma (99. 7% confidence) estimate: 4. 5 C 3 s = x ± ------- [1 + 0. 44 Ns x (1 - x )]1/2 Ns Where Ns is sample size and x is the measured fault coverage in the sample. Example: A circuit with 39, 096 faults has an actual fault coverage of 87. 1%. The measured coverage in a random sample of 1, 000 faults is 88. 7%. The above formula gives an estimate of 88. 7% 3%. CPU time for sample simulation was about 10% of that for all faults. ± 2003 Agrawal: Digital Test and DFT 35

Summary: Fault Sim. n n Fault simulator is an essential tool for test development. Concurrent fault simulation algorithm offers the best choice. For restricted class of circuits (combinational and synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency (Section 5. 5. 6. ) For large circuits, the accuracy of random fault sampling only depends on the sample size (1, 000 to 2, 000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator. 2003 Agrawal: Digital Test and DFT 36

Automatic Test-pattern Generation (ATPG) 2003 Agrawal: Digital Test and DFT 37

Functional vs. Structural ATPG 2003 Agrawal: Digital Test and DFT 38

Functional vs. Structural (Continued) n n n Functional ATPG – generate complete set of tests for circuit input-output combinations § 129 inputs, 65 outputs: § 2129 = 680, 564, 733, 841, 876, 926, 749, 214, 863, 536, 422, 912 patterns § Using 1 GHz ATE, would take 2. 15 x 1022 years Structural test: § No redundant adder hardware, 64 bit slices § Each with 27 faults (using fault equivalence) § At most 64 x 27 = 1728 faults (tests) § Takes 0. 000001728 s on 1 GHz ATE Designer gives small set of functional tests – augment with structural tests to boost coverage to 98 + % 2003 Agrawal: Digital Test and DFT 39

Random-Pattern Generation n n 2003 Flow chart for method Use to get tests for 6080% of faults, then switch to D-algorithm or other ATPG for rest Agrawal: Digital Test and DFT 40

Path Sensitization Method Circuit Example 1 Fault Activation 2 Fault Propagation 3 Line Justification 2003 Agrawal: Digital Test and DFT 41

Path Sensitization Method Circuit Example § Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 1 D D 1 0 D 1 2003 Agrawal: Digital Test and DFT 42

Path Sensitization Method Circuit Example § Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because -frontier (chain of D or D) disappears 1 1 D D 1 D 2003 D D D Agrawal: Digital Test and DFT 43

Path Sensitization Method Circuit Example § Final try: path g – i – j – k – L – test found! 0 1 0 D D D 1 1 2003 Agrawal: Digital Test and DFT 44

Sequential Circuits n n A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which n n Methods of sequential circuit ATPG n n 2003 Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Time-frame expansion methods Simulation-based methods Agrawal: Digital Test and DFT 45

Concept of Time-Frames n If the test sequence for a single stuck-at fault contains n vectors, n n n Fault Unknown or given Init. state Comb. block 2003 Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9 -valued logic Vector -n+1 Timeframe -n+1 PO -n+1 State variables Vector -1 Vector 0 Timeframe -1 Timeframe 0 PO -1 PO 0 Agrawal: Digital Test and DFT Next state 46

An Example of Seq. ATPG FF 1 A 2003 s-a-1 B FF 2 Agrawal: Digital Test and DFT 47

Nine-Valued Logic (Muth) 0, 1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X A 0 A X s-a-1 0/1 FF 2 X 0/X X 0/1 X/1 Time-frame -1 2003 X/1 B X Time-frame 0 Agrawal: Digital Test and DFT B FF 1 FF 2 0/1 48

Seq. ATPG Results s 1423 s 5378 s 35932 Total faults 1, 515 4, 603 39, 094 Detected faults 1, 414 3, 639 35, 100 Fault coverage 93. 3% 79. 1% 89. 8% Test vectors 3, 943 11, 571 257 1. 3 hrs. 37. 8 hrs. CPU time HP J 200 256 MB 10. 2 hrs. Ref. : M. S. Hsiao, E. M. Rudnick and J. H. Patel, “Dynamic State Traversal for Sequential Circuit Test Generation, ” ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 5, no. 3, July 2000. 2003 Agrawal: Digital Test and DFT 49

Summary: ATPG n n n Combinational ATPG is significantly more efficient than sequential ATPG. Combinational ATPG tools are commercially available. Design for testability is essential if the circuit is large (million or more gates) and high fault coverage (~95%) is required. 2003 Agrawal: Digital Test and DFT 50

Design for Testability 2003 Agrawal: Digital Test and DFT 51

Definition n n Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits: § Ad-hoc methods § Structured methods: n n n DFT method for mixed-signal circuits: n 2003 Scan Partial Scan Built-in self-test (BIST) Boundary scan Analog test bus Agrawal: Digital Test and DFT 52

Ad-Hoc DFT Methods n Good design practices learnt through experience are used as guidelines: n n n n n Avoid asynchronous (unclocked) feedback. Make flip-flops initializable. Avoid redundant gates. Avoid large fanin gates. Provide test control for difficult-to-control signals. Avoid gated clocks. . Consider ATE requirements (tristates, etc. ) Design reviews conducted by experts or design auditing tools. Disadvantages of ad-hoc DFT methods: n n n 2003 Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary. Agrawal: Digital Test and DFT 53

Scan Design § Circuit is designed using pre-specified design § rules. Test structure (hardware) is added to the verified design: n n n Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. § Use combinational ATPG to obtain tests for all § 2003 testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. Agrawal: Digital Test and DFT 54

Scan Design Rules n n 2003 Use only clocked D-type of flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops. Agrawal: Digital Test and DFT 55

Scan Flip-Flop (SFF) Master latch D Slave latch TC Q Logic overhead MUX SD Q CK D flip-flop CK TC 2003 Master open Slave open Normal mode, D selected t Scan mode, SD selected Agrawal: Digital Test and DFT t 56

Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF) Master latch Slave latch D Q MCK Q D flip-flop SD MCK TCK 2003 overhead TCK MCK TCK Scan mode Logic Normal mode SCK t Agrawal: Digital Test and DFT 57

Adding Scan Structure PI PO Combinational SFF logic SFF SCANOUT SFF TC or TCK SCANIN 2003 Not shown: CK or MCK/SCK feed all SFFs. Agrawal: Digital Test and DFT 58

Comb. Test Vectors PI I 1 I 2 2003 O 2 Combinational SCANIN TC Present state O 1 SCANOUT logic S 1 N 1 S 2 Agrawal: Digital Test and DFT PO N 2 Next state 59

Testing Scan Register n n n 2003 Scan register must be tested prior to application of scan test sequences. A shift sequence 0011. . . of length nsff+4 in scan mode (TC=0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output. Total scan test length: (ncomb + 2) nsff + ncomb + 4 clock periods. Example: 2, 000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocks. Multiple scan registers reduce test length. Agrawal: Digital Test and DFT 60

Scan Overheads n n n 2003 IO pins: One pin necessary. Area overhead: § Gate overhead = [4 nsff/(ng+10 nff)] x 100%, where ng = comb. gates; nff = flip-flops; Example – ng = 100 k gates, nff = 2 k flip-flops, overhead = 6. 7%. § More accurate estimate must consider scan wiring and layout area. Performance overhead: § Multiplexer delay added in combinational path; approx. two gate-delays. § Flip-flop output loading due to one additional fanout; approx. 5 -6%. Agrawal: Digital Test and DFT 61

ATPG Example: S 5378 Original Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II, 200 MHz processor Number of ATPG vectors Scan sequence length 2003 Agrawal: Digital Test and DFT 2, 781 179 0 0. 0% 4, 603 35/49 70. 0% 70. 9% 5, 533 s 414 Full-scan 2, 781 0 179 15. 66% 4, 603 214/228 99. 1% 100. 0% 5 s 585 105, 662 62

Summary: Scan Design n Scan is the most popular DFT technique: n n Advantages: n n n Design automation High fault coverage; helpful in diagnosis Hierarchical – scan-testable modules are easily combined into large scan-testable systems Moderate area (~10%) and speed (~5%) overheads Disadvantages: n n 2003 Rule-based design Automated DFT hardware insertion Combinational ATPG Large test data volume and long test time Basically a slow speed (DC) test Agrawal: Digital Test and DFT 63

Built-In Self-Test (BIST) 2003 Agrawal: Digital Test and DFT 64

BIST Process n n Test controller – Hardware that activates self-test simultaneously on all PCBs Each board controller activates parallel chip BIST Diagnosis effective only if very high fault coverage 2003 Agrawal: Digital Test and DFT 65

Example External XOR LFSR n 2003 Characteristic polynomial f (x) = 1 + x 3 (read taps from right to left) Agrawal: Digital Test and DFT 66

Definitions n n Aliasing – Due to information loss, signatures of good and some bad machines match Compaction – Drastically reduce # bits in original circuit response – lose information Compression – Reduce # bits in original circuit response – no information loss – fully invertible (can get back original response) Signature analysis – Compact good machine response into good machine signature. Actual signature generated during testing, and compared with good machine signature 2003 Agrawal: Digital Test and DFT 67

Example Modular LFSR Response Compacter n 2003 LFSR seed value is “ 00000” Agrawal: Digital Test and DFT 68

Multiple-Input Signature Register (MISR) n n Problem with ordinary LFSR response compacter: § Too much hardware if one of these is put on each primary output (PO) Solution: MISR – compacts all outputs into one LFSR § Works because LFSR is linear – obeys superposition principle § Superimpose all responses in one LFSR – final remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial 2003 Agrawal: Digital Test and DFT 69

Modular MISR Example 2003 Agrawal: Digital Test and DFT 70

Built-in Logic Block Observer (BILBO) n n Combined functionality of D flip-flop, pattern generator, response compacter, & scan chain Reset all FFs to 0 by scanning in zeros 2003 Agrawal: Digital Test and DFT 71

Circuit Initialization n n Full-scan BIST – shift in scan chain seed before starting BIST Partial-scan BIST – critical to initialize all FFs before BIST starts § n Otherwise we clock X’s into MISR and signature is not unique and not repeatable Discover initialization problems by: 1. Modeling all BIST hardware 2. Setting all FFs to X’s 3. Running logic simulation of CUT with BIST hardware 2003 Agrawal: Digital Test and DFT 72

Summary: BIST n n n LFSR pattern generator and MISR response compacter – preferred BIST methods BIST has overheads: test controller, extra circuit delay, Input MUX, pattern generator, response compacter, DFT to initialize circuit & test the test hardware BIST benefits: § At-speed testing for delay & stuck-at faults § Drastic ATE cost reduction § Field test capability § Faster diagnosis during system test § Less effort to design testing process § Shorter test application times 2003 Agrawal: Digital Test and DFT 73

IEEE 1149. 1 Boundary Scan Standard 2003 Agrawal: Digital Test and DFT 74

System Test Logic 2003 Agrawal: Digital Test and DFT 75

Serial Board / MCM Scan 2003 Agrawal: Digital Test and DFT 76

Parallel Board / MCM Scan 2003 Agrawal: Digital Test and DFT 77

Tap Controller Signals n Test Access Port (TAP) includes these signals: § Test Clock Input (TCK) -- Clock for test logic Can run at different rate from system clock Test Mode Select (TMS) -- Switches system from functional to test mode Test Data Input (TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers) Test Reset (TRST) -- Optional asynchronous TAP controller reset n § § 2003 Agrawal: Digital Test and DFT 78

Summary: Bound. Scan n Functional test: verify system hardware, software, function and performance; pass/fail test with limited diagnosis; high (~100%) software coverage metrics; low (~70%) structural fault coverage. Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree. SOC design for testability: n n n 2003 Partition SOC into blocks of logic, memory and analog circuitry, often on architectural boundaries. Provide external or built-in tests for blocks. Provide test access via boundary scan and/or analog test bus. Develop interconnect tests and system functional tests. Develop diagnostic procedures. Agrawal: Digital Test and DFT 79

IDDQ Test 2003 Agrawal: Digital Test and DFT 80

Basic Principle of IDDQ Testing 2003 § Measure IDDQ current through Vss bus Agrawal: Digital Test and DFT 81

Capacitive Coupling of Floating Gates n n n 2003 Cpb – capacitance from poly to bulk Cmp – overlapped metal wire to poly Floating gate voltage depends on capacitances and node voltages If n. FET and p. FET get enough gate voltage to turn them on, then IDDQ test detects this defect K is the transistor gain Agrawal: Digital Test and DFT 82

Sematech Results Scan-based Stuck-at n Test process: Wafer Test Package Test Burn-In & Retest Characterize & Failure Analysis Data for devices failing some, but not all, tests. 2003 IDDQ (5 m. A limit) pass fail pass 6 14 0 6 1 52 36 pass fail 1463 34 13 1251 pass Functional Agrawal: Digital Test and DFT fail 7 pass 1 pass 8 fail Scan-based delay n 83

Summary: IDDQ Test n n 2003 IDDQ tests improve reliability, find defects causing: § Delay, bridging, weak faults § Chips damaged by electro-static discharge No natural breakpoint for current threshold § Get continuous distribution – bimodal would be better Conclusion: now need stuck-fault, IDDQ, and delay fault testing combined Still uncertain whether IDDQ tests will remain useful as chip feature sizes shrink further Agrawal: Digital Test and DFT 84

References n M. L. Bushnell and V. D. Agrawal, Essentials n Kluwer Academic Publishers, 2000, ISBN 0 -7923 -7991 -8. For the material on a course taught by the authors at Rutgers University, and a complete bibliography from the above book, see website: of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston: http: //cm. bell-labs. com/cm/cs/who/va 2003 Agrawal: Digital Test and DFT 85