COS 2014 IA32 Processor Architecture Overview Goal Understand

COS 2014 IA-32 Processor Architecture

Overview Goal: Understand IA-32 architecture u Basic Concepts of Computer Organization l l u u Instruction execution cycle Basic computer organization Data storage in memory How programs run IA-32 Processor Architecture IA-32 Memory Management Components of an IA-32 Microcomputer Input-Output System 1

Recall: Computer Model for ASM MOV AX, a ADD AX, b MOV x, AX … CPU PC AX BX Register x a+b Memory a 01010010101 b 110010110001010 x 0000010010 . . . ALU + - 2

Meanings of the Code (assumed) Assembly code MOV AX, a (Take the data stored in memory address ‘a’, and move it to register AX) ADD AX, b (Take the data stored in memory address ‘b’, and add it to register AX) MOV x, AX Machine code 01 0000001 1000010 MOV register address AX memory address a 11 0000001 1000110 ADD 01 1000011 0000001 (Take the data stored in register AX, and move it to memory address ‘x’) 3

Another Computer Model for ASM Processor AX BX … Stored program architecture x a data b 01 0000001 1000010 MOV AX, a 11 0000001 1000110 ADD AX, b 01 1000011 0000001 MOV x, AX … ALU IR Memory Register PC address PC: program counter IR: instruction register 4

Step 1: Fetch (MOV AX, a) Register AX BX … Memory x a data b 01 0000001 1000010 MOV AX, a 11 0000001 1000110 ADD AX, b 01 1000011 0000001 MOV x, AX … ALU IR PC 01 0000001 1000010 0000111 address 5

Step 2: Decode (MOV AX, a) Register AX BX … Memory x a data b 01 0000001 1000010 MOV AX, a 11 0000001 1000110 ADD AX, b 01 1000011 0000001 MOV x, AX … Controller ALU clock IR PC 01 0000001 1000010 0000111 address 6

Step 3: Execute (MOV AX, a) Register AX BX Memory 00000001 … data x 000000001 a b 01 0000001 1000010 MOV AX, a 11 0000001 1000110 ADD AX, b 01 1000011 0000001 MOV x, AX … Controller ALU clock IR PC 01 0000001 1000010 0000111 address 7

Step 1: Fetch (ADD AX, b) Register AX BX Memory 00000001 … x a data b 01 0000001 1000010 MOV AX, a 11 0000001 1000110 ADD AX, b 01 1000011 0000001 MOV x, AX … ALU IR PC 11 0000001 1000110 0001000 address 8

Step 2: Decode (ADD AX, b) Register AX BX Memory 00000001 … x a data b 01 0000001 1000010 MOV AX, a 11 0000001 1000110 ADD AX, b 01 1000011 0000001 MOV x, AX … Controller ALU clock IR PC 11 0000001 1000110 0001000 address 9

Step 3 a: Execute (ADD AX, b) Register AX BX Memory 00000001 … x a data b 00000010 01 0000001 1000010 MOV AX, a 11 0000001 1000110 ADD AX, b 01 1000011 0000001 MOV x, AX Controller + ALU … 00000011 clock IR PC 11 0000001 1000110 0001000 address 10

Step 3 b: Write Back (ADD AX, b) Register AX BX Memory 00000011 00000001 … x a data b 01 0000001 1000010 MOV AX, a 11 0000001 1000110 ADD AX, b 01 1000011 0000001 MOV x, AX … Controller ALU 00000011 clock IR PC 11 0000001 1000110 0001000 address 11

Basic Computer Organization u u u Clock synchronizes CPU operations Control unit (CU) coordinates execution sequence ALU performs arithmetic and bitwise processing 12

Clock u u Operations in a computer are triggered and thus synchronized by a clock Clock tells “when”: (no need to ask each other!!) l l u When to put data on output lines When to read data from input lines Clock cycle measures time of a single operation l Must long enough to allow signal propagation 13

Instruction/Data for Operations u u Where are the instructions needed for computer operations from? Stored-program architecture: l l l u The whole program is stored in main memory, including program instructions (code) and data CPU loads the instructions and data from memory for execution Don’t worry about the disk for now Where are the data needed for execution? l l l Registers (inside the CPU, discussed later) Memory Constant encoded in the instructions 14

Memory u Organized like mailboxes, numbered 0, 1, 2, 3, …, 2 n-1. l l u Each box can hold 8 bits (1 byte) So it is called byte-addressing Address of mailboxes: l l l 16 -bit address is enough for up to 64 K 20 -bit for 1 M 32 -bit for 4 G Most servers need more than 4 G!! That’s why we need 64 -bit CPUs like Alpha (DEC/Compaq/HP) or Merced (Intel) … l 15

Storing Data in Memory u Character String: l l u So how are strings like “Hello, World!” are stored in memory? ASCII Code! (or Unicode…etc. ) Each character is stored as a byte Review: how is “ 1234” stored in memory? Integer: l A byte can hold an integer number: ‒ between 0 and 255 (unsigned) or ‒ between – 128 and 127 (2’s complement) l l How to store a bigger number? Review: how is 1234 stored in memory? 16

Big or Little Endian? u u Example: 1234 is stored in 2 bytes. = 100 1101 0010 in binary = 04 D 2 in hexadecimal Do you store 04 or D 2 first? Big Endian: 04 first Little Endian: D 2 first Intel’s choice l Reason: more consistent for variable length (e. g. , 2 bytes, 4 bytes, 8 bytes…etc. ) 17

Cache Memory u High-speed expensive static RAM both inside and outside the CPU. l l u u Level-1 cache: inside the CPU chip Level-2 cache: often outside the CPU chip Cache hit: when data to be read is already in cache memory Cache miss: when data to be read is not in cache memory 18

How a Program Runs? 19

Load and Execute Process u u u u OS searches for program’s filename in current directory and then in directory path If found, OS reads information from directory OS loads file into memory from disk OS allocates memory for program information OS executes a branch to cause CPU to execute the program. A running program is called a process Process runs by itself. OS tracks execution and responds to requests for resources When the process ends, its handle is removed and memory is released How? OS is only a program! 20

Multitasking u u OS can run multiple programs at same time Multiple threads of execution within the same program Scheduler utility assigns a given amount of CPU time to each running program Rapid switching of tasks l l Gives illusion that all programs are running at the same time Processor must support task switching What supports are needed from hardware? 21

What's Next u u General Concepts IA-32 Processor Architecture l l u u u Modes of operation Basic execution environment Floating-point unit Intel microprocessor history IA-32 Memory Management Components of an IA-32 Microcomputer Input-Output System 22

Modes of Operation u Protected mode l l u Real-address mode l u native mode (Windows, Linux) Programs are given separate memory areas named segments native MS-DOS System management mode l power management, system security, diagnostics • Virtual-8086 mode - hybrid of Protected - each program has its own 8086 computer 23

Basic Execution Environment Address space: u Protected mode l l u 4 GB 32 -bit address Real-address and Virtual-8086 modes l l 1 MB space 20 -bit address 24

Basic Execution Environment u Program execution registers: named storage locations inside the CPU, optimized for speed Register Memory Controller clock N Z IR ALU PC 25

General Purpose Registers u u Used for arithmetic and data movement Addressing: l AX, BX, CX, DX: 16 bits l Split into H and L parts, 8 bits each Extended into E? X to become 32 -bit register (i. e. , EAX, EBX, …etc. ) l 26

Index and Base Registers u Some registers have only a 16 -bit name for their lower half: 27

Some Specialized Register Uses u General purpose registers l l l u EAX: accumulator, automatically used by multiplication and division instructions ECX: loop counter ESP: stack pointer ESI, EDI: index registers (source, destination) for memory transfer, e. g. a[i, j] EBP: frame pointer to reference function parameters and local variables on stack EIP: instruction pointer (i. e. program counter) 28

Some Specialized Register Uses u Segment registers l l l u In real-address mode: indicate base addresses of preassigned memory areas named segments In protected mode: hold pointers to segment descriptor tables CS: code segment DS: data segment SS: stack segment ES, FS, GS: additional segments EFLAGS l l Status and control flags (single binary bits) Control the operation of the CPU or reflect the outcome of some CPU operation 29

Status Flags (EFLAGS) Reflect the outcomes of arithmetic and logical operations performed by the CPU u Carry: unsigned arithmetic out of range u Overflow: signed arithmetic out of range u Sign: result is negative u Zero: result is zero u Auxiliary Carry: carry from bit 3 to bit. Register 4 u Parity: sum of 1 bits is an even number Memory Controller clock N Z IR ALU PC 30

System Registers Application programs cannot access system registers u IDTR (Interrupt Descriptor Table Register) u GDTR (Global Descriptor Table Register) u LDTR (Local Descriptor Table Register) u Task Register u Debug Registers u Control registers CR 0, CR 2, CR 3, CR 4 u Model-Specific Registers 31

Floating-Point, MMX, XMM Reg. u Eight 80 -bit floating-point data registers l l l u u ST(0), ST(1), . . . , ST(7) arranged in a stack used for all floating-point arithmetic Eight 64 -bit MMX registers Eight 128 -bit XMM registers for single-instruction multiple-data (SIMD) operations 32

Intel Microprocessors u Early microprocessors: l Intel 8080: ‒ 64 K addressable RAM, 8 -bit registers ‒ CP/M operating system ‒ S-100 BUS architecture ‒ 8 -inch floppy disks! l Intel 8086/8088 ‒ IBM-PC used 8088 ‒ 1 MB addressable RAM, 16 -bit registers ‒ 16 -bit data bus (8 -bit for 8088) ‒ separate floating-point unit (8087) This is where “real-address mode” comes from! 33

Intel Microprocessors u The IBM-AT Intel l 80286 ‒ 16 MB addressable RAM ‒ Protected memory ‒ Introduced IDE bus architecture ‒ 80287 floating point unit u Intel IA-32 Family l l l Intel 386: 4 GB addressable RAM, 32 -bit registers, paging (virtual memory) Intel 486: instruction pipelining Pentium: superscalar, 32 -bit address bus, 64 -bit internal data path 34

Intel Microprocessors u Intel P 6 Family l l Pentium Pro: advanced optimization techniques in microcode Pentium II: MMX (multimedia) instruction set Pentium III: SIMD (streaming extensions) instructions Pentium 4 and Xeon: Intel Net. Burst microarchitecture, tuned for multimedia 35

What’s Next u u u General Concepts of Computer Architecture IA-32 Processor Architecture IA-32 Memory Management l l l u u Real-address mode Calculating linear addresses Understand it from Protected mode the view point of the processor Multi-segment model Paging Components of an IA-32 Microcomputer Input-Output System 36

Real-address Mode u u Programs assigned 1 MB (220) of memory Programs can access any area of memory Can run only one program at a time Segmented memory scheme l l l 16 -bit segment * 10 h + 16 -bit offset = 20 -bit linear (or absolute) address Segment value in CS, SS, DS, ES Offset value in IP, SP, BX & SI, DI

Example u Accessing a variable in the data segment l l u DS (data segment) = 0 A 43 BX (offset) = 0030 (16 -bits) 0 A 43 * 10 = 0 A 430 (20 -bits) + 0030 (16 -bits) 0 A 460 (linear address)

Segmented Memory Segmented memory addressing: absolute (linear) address is a combination of a 16 -bit segment value (in CS, DS, SS, or ES) added to a 16 -bit offset linear addresses u one segment represented as 8000 0000 segment value offset 39

Calculating Linear Addresses u u Given a segment address, multiply it by 16 (add a hexadecimal zero), and add it to the offset all done by the processor Example: convert 08 F 1: 0100 to a linear address Adjusted Segment value: 0 8 F 1 0 Add the offset: 0 1 0 0 Linear address: 0 9 0 1 0 40

Protected Mode u u u Designed for multitasking Each process (running program) is assigned a total of 4 GB of addressable RAM Two parts: l l Segmentation: provides a mechanism of isolating individual code, data, and stack so that multiple programs can run without interfering one another Paging: provides demand-paged virtual memory where sections of a program’s execution environ. are moved into physical memory as needed Give segmentation the illusion that it has 4 GB of physical memory 41

Segmentation in Protected Mode u Segment: a logical unit of storage (not the same as the “segment” in real-address mode) l l l e. g. , code/data/stack of a program, system data structures Variable size Processor hardware provides protection All segments in the system are in the processor’s linear address space (physical space if without paging) Need to specify: base address, size, type, … segment descriptor & descriptor table linear address = base address + offset 42

Flat Segment Model u u Use a single global descriptor table (GDT) All segments (at least 1 code and 1 data) mapped to entire 32 -bit address space 43

Multi-Segment Model u Local descriptor table (LDT) for each program l One descriptor for each segment located in a system segment of LDT type 44

Segmentation Addressing u Program references a memory location with a logical address: segment selector + offset l l Segment selector: provides an offset into the descriptor table CS/DS/SS points to descriptor table for code/data/stack segment 45

Convert Logical to Linear Address Segment selector points to a segment descriptor, which contains base address of the segment. The 32 -bit offset from the logical address is added to the segment’s base address, generating a 32 -bit linear address 46

Paging u u u Supported directly by the processor Divides each segment into 4096 -byte blocks called pages Part of running program is in memory, part is on disk l u u Sum of all programs can be larger than physical memory Virtual memory manager (VMM): An OS utility that manages loading and unloading of pages Page fault: issued by processor when a page must be loaded from disk 47

What's Next u u General Concepts IA-32 Processor Architecture IA-32 Memory Management Components of an IA-32 Microcomputer l u Skipped … Input-Output System 48

What's Next u u u General Concepts IA-32 Processor Architecture IA-32 Memory Management Components of an IA-32 Microcomputer Input-Output System l How to access I/O systems? 49

Different Access Levels of I/O u Call a HLL library function (C++, Java) l l u Call an operating system function l l u specific to one OS; device-independent medium performance Call a BIOS (basic input-output system) function l l l u easy to do; abstracted from hardware slowest performance may produce different results on different systems knowledge of hardware required usually good performance Communicate directly with the hardware l May not be allowed by some operating systems 50

Displaying a String of Characters u When a HLL program displays a string of characters, the following steps take place: l l l Calls an HLL library function to write the string to standard output Library function (Level 3) calls an OS function, passing a string pointer OS function (Level 2) calls a BIOS subroutine, passing ASCII code and color of each character BIOS subroutine (Level 1) maps the character to a system font, and sends it to a hardware port attached to the video controller card Video controller card (Level 0) generates timed hardware signals to video display to display pixels 51

IA-32: Addressing Modes IA-32 machine instructions act on zero or more operands. Some operands are specified explicitly in an instruction whereas other operands are implicit in an instruction. The data for a source operand can be located in any of the following places –The instruction itself (immediate operand) –A register –A memory location –An I/O Port

ตวอยาง – MOV EAX, 5 ; Moves into the EAX register the value 5 – MOV EBX, EAX ; Moves into register EBX the value of register EAX – MOV [EBX], EAX ; Moves into the memory address pointed to by EBX the value EAX

The IA-32 provides a total of seven distinct addressing modes: –register –immediate –direct –register indirect –based relative –indexed relative –based indexed relative

1. Register Addressing Mode Examples of register addressing mode follow: – MOV BX, DX ; copy contents of register BX into register DX – MOV ES, AX ; copy contents of register AX into segment register ES – MOV EDX, ESI ; copy contents of register ESI into register EDX

Basic Operand Types Register Operands u Very efficient Examples u inc ECX u mov BX, AX mov SI, 10

– 2. Immediate Addressing Mode – Examples: – MOV AX, 2550 h ; move value 2550 h into the AX register – MOV ESI, 12345678 h ; move value 12345678 h into the ESI register – MOV BL, 40 h ; move value 40 h into the BL register

Basic Operand Types Immediate Operands u u Immediate operands are constants Examples add mov u u AX, 10 BL, 'a' BL, 61 h Numbers do not have a length attribute. For example, we can add 10 to AH, AX, and EAX. Of course the immediate value fit in the destination mov AL, 12345678 h ; Illegal

To move information to the segment registers, the data must first be moved to a general-purpose register and then into the segment registers. Example: – real-address mode: – MOV AX, 2550 h ; AX contains the segment address – MOV DS, AX ; load the DS segment register with AX – protected mode: – MOV AX, 08 h ; AX contains the segment selector – MOV DS, AX ; load the DS segment register with AX

3. Direct Addressing Mode – real-address mode: – MOV DL, [2400 h] ; moves content of DS: 2400 h into DL register – MOV AX, [5500 h] ; moves content of DS: 5500 h into the AX register – protected mode: – MOV EAX, [12345678 h] ; moves content of DS: 12345678 h into the EAX register

Basic Operand Types Direct Operands u u u Allows accessing memory variables by name Slower because memory is "slow" Example mov DX, w. Val 1 add DX, w. Val 2 mov w. Data, DX

4. Register Indirect Addressing Mode – real-address mode: – MOV AL, [BX] ; moves into AL the contents of the memory location pointed to by DS: BX – MOV [DI], AL ; moves into DS: DI the contents of the register AL – protected mode: – MOV AL, [EAX] ; moves into AL the contents of the memory location pointed to by DS: EAX – MOV [EBX], ESI ; moves into DS: EBX the contents of the register ESI – MOV BL, [ESI] ; moves into BL the contents of the memory location pointed to by DS: ESI

Indirect Addressing Modes u mov AX, [ESI] ESI 26 AX 600 Memory 24 26 28 2 A 2 C 2 E 30 600

Indirect Addressing Modes: Example u u . data List DWORD 1, 3, 10, 6, 2, 9, 2, 8, 9 Number = ($ - List)/4 or LENGTHOF List. code … ; sum values in list mov EAX, 0 ; sum = 0 mov ECX, Number ; number of values mov ESI, OFFSET List ; ptr to List L 3: add EAX, [ESI] ; add value add ESI, 4 ; point to next value loop L 3 ; repeat as needed

Indirect Addressing Modes u String BYTE "the words" Long = $ - String or LENGTHOF String … ; Print string 1 character at a time ; using Write. Char mov ECX, Long ; ECX <- number char mov ESI, OFFSET String; pt to string L 9: mov AL, [ESI] ; get char. call Write. Char ; print char inc ESI ; point to next char loop L 9 ; repeat

5. Based Relative Addressing Mode – In real-address mode, base registers BX and BP , as well as a displacement value, are used to calculate what is called an effective address. The default segment registers used for the calculation of the physical address are DS for BX and SS for BP. Example: – MOV CX, [BX+10 h] ; moves 16 -bit word at DS: BX+10 h into CX register – MOV [BP+22 h], CX ; moves contents of CX register into memory location SS: BP+22 h

– In case of protected mode, registers EAX, EBX, ECX, EDX, ESI, EDI, EBP and ESP can be used as base registers. The default segment registers used for calculation of physical address are DS for EAX, EBX, ECX, EDX, ESI and EDI and SS for EBP and ESP. – MOV EAX, [EBX+10 h] ; moves 32 -bit quantity at DS: EBX+10 h into the EAX register – MOV [EBP+22 h], EDX ; moves contents of EDX register into memory location SS: EBP+22 h

6. Indexed Relative Addressing Mode In real-address mode, index registers SI and DI , as well as a displacement value, are used to calculate what is called an effective address. The default segment register used for the calculation of the physical address is the DS register. MOV CX, [SI+10 h] ; moves 16 -bit word at DS: SI+10 h into CX register – MOV [DI+22 h], CX ; moves contents of CX register into memory location DS: DI+22 h – MOV EAX, [ESI+10 h] ; moves 32 -bit quantity at DS: ESI+10 h into the EAX register

– In case of protected mode, registers EAX, EBX, ECX, EDX, ESI, EDI, EBP and ESP can be used as index registers. The default segment registers used for calculation of physical address are DS for EAX, EBX, ECX, EDX, ESI and EDI and SS for EBP and ESP. – MOV EAX, [ESI+10 h] ; moves 32 -bit quantity at DS: ESI+10 h into the EAX register – MOV [EDI+22 h], EDX ; moves contents of EDX register into memory location DS: EDI+22 h

7. Based Indexed Addressing Mode – Examples: – real-address mode: – MOV CL, [BX+SI+8 h] ; moves into CL register, byte at memory location DS: BX+SI+8 h – MOV CL, [BX+DI+8 h] ; moves into CL register, byte at memory location DS: BX+DI+8 h – MOV CL, [BP+SI+8 h] ; moves into CL register, byte at memory location SS: BP+SI+8 h – MOV CL, [BP+DI+8 h] ; moves into CL register, byte at memory location DS: BP+DI+8 h

– protected mode: – MOV CL, [EBX+EAX+10 h] ; moves into CL register, byte at memory location DS: EBX+EAX+10 h – MOV CL, [EBP+EAX+10 h] ; moves into CL register, byte at memory location SS: EBP+EAX+10 h – MOV CL, [ESI+EDI+10 h] ; moves into CL register, byte at memory location DS: ESI+EDI+10 h

– Segment overrides and 32 -bit scaling factors – MOV CX, ES: [SI+10 h] ; moves 16 -bit word at ES: SI+10 h into CX register – In case of 32 -bit instructions, we can also add a scaling factor in any of the based, indexed or based indexed addressing modes. The scaling factor must always be a power of 2. Example : – MOV EAX, [ESI + EAX*4] ; moves into EAX the 32 -bit quantity at DS: ESI+EAX*4

Indirect Addressing Based and Indexed Addressing u mov ESI 4 AX 100 Memory AX, List[ESI] List+2 List+4 List+6 List+8 List+10 List+12 100

Indirect Addressing Based and Indexed Addressing u mov ESI, OFFSET List AX, [ESI+4] OFFSET List AX 100 List+2 List+4 List+6 List+8 List+10 List+12 Memory 100

Indirect Addressing Based - Indexed Addressing u mov mov EBX, OFFSET List ESI, 4 AX, [EBX+ESI] EBX OFFSET List + ESI 4 AX 100 List+2 List+4 List+6 List+8 List+10 List+12 Memory 100

Summary u u u u u Central Processing Unit (CPU) Arithmetic Logic Unit (ALU) Instruction execution cycle Multitasking Floating Point Unit (FPU) Complex Instruction Set Real mode and Protected mode Motherboard components Memory types Input/Output and access levels 77