Chapter 5 STM Arm Timer Programming 1 A

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Chapter 5 STM Arm Timer Programming 1

Chapter 5 STM Arm Timer Programming 1

A 3 -bit Counter 2

A 3 -bit Counter 2

An 8 -bit up-counter stages 3

An 8 -bit up-counter stages 3

An 8 -bit down-counter stages 4

An 8 -bit down-counter stages 4

Counting Events Using a Counter 5

Counting Events Using a Counter 5

Using Counter as a Timer 6

Using Counter as a Timer 6

Capturing 7

Capturing 7

System Tick Timer Internal Structure 8

System Tick Timer Internal Structure 8

STCTRL (System Tick Control) 9

STCTRL (System Tick Control) 9

System Tick Counting 10

System Tick Counting 10

STRELOAD vs. STCURRENT 11

STRELOAD vs. STCURRENT 11

STMF 466 RE Arm timers 12

STMF 466 RE Arm timers 12

STM 32 F 4 xx Timer Prescale Options 13

STM 32 F 4 xx Timer Prescale Options 13

RCC_APB 1 ENR Register is used to enable timer clock 14

RCC_APB 1 ENR Register is used to enable timer clock 14

RCC_APB 2 ENR Register is used to enable timer clock 15

RCC_APB 2 ENR Register is used to enable timer clock 15

Some of the STM 32 F 4 xx Timer Registers 16

Some of the STM 32 F 4 xx Timer Registers 16

CR 1 (Control 1) Register 17

CR 1 (Control 1) Register 17

Some of the CR 1 register bits 18

Some of the CR 1 register bits 18

TIMx. SR Register 19

TIMx. SR Register 19

TIMx_SR (Staus) Register UIF Bit 20

TIMx_SR (Staus) Register UIF Bit 20

TIMx counter (TIMx_CNT) 21

TIMx counter (TIMx_CNT) 21

TIMx auto-reload register (TIMx_ARR) 22

TIMx auto-reload register (TIMx_ARR) 22

TIM 2_CNT counter counting for 32 -bit 23

TIM 2_CNT counter counting for 32 -bit 23

TIMx prescaler (TIMx_PSC) 24

TIMx prescaler (TIMx_PSC) 24

TIMx Options for Prescaler 25

TIMx Options for Prescaler 25

CNT, ARR and Compare registers (CCR) with Waveform Output 26

CNT, ARR and Compare registers (CCR) with Waveform Output 26

TIMx capture/compare registers (TIMx_CCRy) 27

TIMx capture/compare registers (TIMx_CCRy) 27

TIMx_CCMR 1 for output option 28

TIMx_CCMR 1 for output option 28

TIMx_CCMR 2 for output option OCx. CE: Output compare x clear enable OCx. M:

TIMx_CCMR 2 for output option OCx. CE: Output compare x clear enable OCx. M: Output compare x mode The OCx. M options for output pin: 000: 001: 010: 011: 100: 101: 110: 111: bits in TIMx_CCMRy register are used to decide the output operation. Here are the Frozen Set output to active HIGH level when TIMx_CNT=TIMx_CCRy. Set output to inactive LOW level when TIMx_CNT=TIMx_CCRy. Toggle when TIMx_CNT=TIMx_CCRy. Forced LOW. Forced HIGH. PWM mode 1. (See Chapter 11) PWM mode 2. (See Chapter 11) OCx. PE: Output compare x preload enable CCx. S: Capture/Compare x selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CCx channel is configured as output 29

TIMx_CCER (TIMx capture/compare enable register) 30

TIMx_CCER (TIMx capture/compare enable register) 30

MODER Register is used to select alternative pin functions 31

MODER Register is used to select alternative pin functions 31

GPIOx_AFRL Register 32

GPIOx_AFRL Register 32

STMF 466 RE Alternative Function Table for Ports A and B (See Appendix B

STMF 466 RE Alternative Function Table for Ports A and B (See Appendix B for other Ports) 33

TIM_CCER Register (Notice the input capture) 34

TIM_CCER Register (Notice the input capture) 34

TIMx_CCMR 1 and TIMx_CCMR 2 (register details are shown in the last section) 35

TIMx_CCMR 1 and TIMx_CCMR 2 (register details are shown in the last section) 35

Inputing Signal 36

Inputing Signal 36

Messuring Period and Puls Width 37

Messuring Period and Puls Width 37

Counting Pulses 38

Counting Pulses 38