AT 91 ARM 7 ARM 9 MICROCONTROLLERS ARM

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AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Processor 1

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Processor 1

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Processor • The

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Processor • The ARM 920 T processor is a member of the ARM 9 TDMI family of general purpose microprocessors – Includes the ARM 9 TDMI core plus cache and MMU. • ARM 9 TDMI processor: – Harvard architecture • Increases available memory bandwith • Simultaneous access to instruction and data memory can be achieved – 5 -stage pipeline – 32 -bit ARM instruction set and 16 -bit THUMB instruction set. 2

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Processor • ARM

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Processor • ARM 7 TDMI Instruction Fetch Thumb ARM decode decompress Reg Select FETCH DECODE Reg Read Shift ALU Reg Write EXECUTE • ARM 9 TDMI Instruction Fetch ARM or Thumb Inst Decode Reg Decode Read Shift + ALU Memory Access Reg Write FETCH DECODE EXECUTE MEMORY WRITE 3

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Processor • Cached

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Processor • Cached Processor for Platform OS Applications – 16 K Instruction & Data Caches – ARMv 4 MMU for: Palm. OS, EPOC, Linux & Windows. CE – Includes support for Coprocessor and ETM 16 K I Cache ARM 9 TDMI CORE 16 K D Cache MMU Write Buffer MMU Control Logic & BIU Coprocessor, ETM 9 & AMBA ASB Interfaces 4

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • What

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • What is an MMU ? – Memory Management Unit • Controls memory access permissions • Translates virtual addresses into physical addresses – MMU consists of • Translation Look-aside Buffer (TLB) – Cache of recently used page translations • Hardware for page table walks – Updates TLB • Access control logic – If MMU is disabled • External address bus will output virtual addresses directly 5

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • Virtual

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • Virtual to Physical Address Mapping Virtual Memory Process D Translation and checking mechanism. MMU Process C Process B Process A Physical Memory Translation Tables VRAM I TLB D TLB RAM ROM RAM RAM Manager Protection & Aborts 6

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • Translation

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • Translation Look-aside Buffer acts as a cache of recent VA to PA translations – Provides translation and access permission information for most memory accesses – For TLB misses, the translation table walking hardware retrieves the information from the translation table in physical memory and the TLB is updated – If the TLB is full, a value will be overwritten using a cyclic scheme – Translation Tables resides in physical memory – Level 1 table is a list of 4096 translations, indexed by bits 31: 20 of the virtual address – Entries contain a pointer to a 1 MB section of physical memory along with attribute information, or … – A pointer to the base address of a another table, containing pointers to smaller pages of physical memory 7

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • Translation

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • Translation Process – Performed by hardware and is transparent to the user • Translation tables created by software Virtual address Check if TLB contains virtual address yes Get physical address no Do translation table walk Get physical address Update TLB 8

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • •

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • • • Two Translation Lookaside Buffers (TLBs) • 64 -entry Instruction TLB • 64 -entry Data TLB Two-level Hardware table walking : • Address translation • Access control logic with permissions Highly flexible mapping scheme - supports: • 1 MB sections (with permissions) • 64 k. B large pages (permissions for each subpage of a page) • 4 k. B small pages (permissions for each subpage of a page) • 1 k. B tiny pages (with permissions) 9

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • MMU

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T MMU • MMU usage in Linux – Allows Memory mapping (physical to virtual address) – Allows memory allocation – Allows to safely run several processes, each one has a protected memory area. – Provides protection against direct access to a peripheral’s physical address 10

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Caches • What

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Caches • What is a cache ? – – – Small fast memory, local to the processor Holds copies of recently accessed memory locations Relies on memory re-use Only improves performance for slow memory or narrow memory Reduces bus bandwidth requirements Reduces power consumption Address Cache CPU Bus Interface Data External Memory 11

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Caches • •

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Caches • • • 16 KB instruction and data caches 512 lines of 8 words arranged as a 64 -way set-associative cache MMU must be enabled to enable Dcache TAG = MVA [ 31 : 8 ] TAG 8 words 8 8 words 7 8 words 6 8 words 5 8 words 4 8 words 3 8 words 2 8 words 1 64 lines 12

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Caches • Cache

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Caches • Cache hit and miss – Cache hit, if region is cachable, data are returned from the cache – Cache miss, an eight-word linefill is performed replacing another entry – Replacement algorithm – Random by default – Round-Robin : entries of each segment are replaced sequentially. More efficient. • Caches operate at processor speed – Max processor speed is 180 Mhz – Max AMBA ASB speed is 60 Mhz 13

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Caches – 16

AT 91 ARM 7 & ARM 9 MICROCONTROLLERS ARM 920 T Caches – 16 -word (64 Bytes) write buffer • Lockdown features – Lockdown instruction and data caches independently with a granularity of 1/64 th of cache – Must lockdown the associated TLB entry in the TLB to avoid page table walks during accesses to the locked data or instruction – Provide optimum and predictable execution time 14