Wireless Transceiver EECS 150 Spring 2008 Shah Bawany

Wireless Transceiver EECS 150 Spring 2008 Shah Bawany 9/18/2021 EECS 150 Spring 2008 1

This Lab Lecture… n n n 9/18/2021 Timeline Checkpoint 3 Overview Checkpoint 2. 5 Overview EECS 150 Spring 2008 2

Timeline n Checkpoint 1 n n n Checkpoint 2 n n n 9/18/2021 Was due this week If you didn’t finish, turn it in as soon as you do for partial credit Design Reviews were this week Code due after break Very easy checkpoint, but we are only postponing the due date so you can make thoughtful designs for checkpoint 3 (we will grade them much more harshly) and so that you can catch up if you’ve fallen behind (by working all break EECS 150 Spring 2008 3

Timeline (2) n Checkpoint 2. 5: 4 -Port Arbiter, Frame Subsampling, Complete UI n n Checkpoint 3: Wireless Transceiver n n n 9/18/2021 An early start on Checkpoint 4 for those looking to work ahead. If you make a design for the CP 3 design review AND get checked off for it with CP 3, you will get 5% extra credit on CP 3. Specs will be up this weekend Specs up now, Design Reviews next week Due the week after CP 2 (the 2 nd week after break) The time given for this checkpoint is justified by its difficulty EECS 150 Spring 2008 4

Timeline (3) n Checkpoint 3 (continued) n Some additional tools will be released this weekend or early next week n n n Checkpoint 4: Integration and Compression n n 9/18/2021 Packet sniffer - For detecting what’s being transmitted on a wireless channel) TA solution - To test transmit / receive independently Specs will hopefully be up before break Lab lecture will be the week you return from break Design reviews will be the same week CP 3 is due Final project (CP 4 + extra credit) due 2 weeks after CP 4 design reviews EECS 150 Spring 2008 5

Transceiver Overview (1) n 3 rd party chip mounted on expansion board. n n n IEEE 802. 15. 4 standard support. Transmits on unlicensed 2. 4 GHz spectrum. 16 communication channels. n n 9/18/2021 Overlaps with Wi-Fi. 250 kbps maximum data rate. n n Uses a PCB antenna. Take a look! In use in the project, we can achieve 16 KBps Configure, send, receive, and issue commands to chip over SPI to CC 2420 registers. EECS 150 Spring 2008 6

Transceiver Overview (2) n 33 configuration registers. n n 15 command strobe registers. n n n We issue 6 of them. These change the state of the CC 2420 internal FSM. 128 -byte RX FIFO & 128 -byte TX FIFO n n 9/18/2021 We change 3 of them. Accessed via 2 additional registers. Also accessible as RAM (i. e. by addressing). Only for debugging! Don’t do this unless you’re a masochist EECS 150 Spring 2008 7

Transceiver Overview (3) n You will need to read the data sheet to learn more about how the CC 2420 works in more detail than what we can fit in the Spec. n n 9/18/2021 MDPU Status Registers (more info. ) Commands (more info. ) Internal state machine (very helpful!!) EECS 150 Spring 2008 8

CC 2420 Inputs & Outputs n Single bit status signals. n FPGA n Initialization signals. n VREG_EN RF_RESET_ n Drive signals once and forget about it. SPI interface. n n 9/18/2021 High level transceiver operation information. Interface to rest of chip via CC 2420 registers. Send, receive, configuration, detailed status. EECS 150 Spring 2008 9

Single Bit Status Indicators n n 9/18/2021 FIFO – Goes high when there’s received data in RX FIFOP – Goes high when # bytes received exceeds set threshold. CCA – Indicates that the transmission medium (air) is clear. Only valid after 8 symbol periods in RX mode. SFD – Goes high after SFD is transmitted & low after packet completely sent. EECS 150 Spring 2008 10

SPI Interface n Serial interface with 4 wires: n n n 9/18/2021 SClk – Clock signal you generate. CS_ – Active-low chip select. SI – Output to the CC 2420. SO – Input from the CC 2420. Interface to the chip! Initialization, configuration, TX, RX, detailed status. Luckily for you, it’s provided as a black box. EECS 150 Spring 2008 11

CC 2420 -specific SPI (1): First Byte Sent First 7 Bit Position 6 5: 0 1 = RAM access (not used) 1 = read 0 = register access 0 = write n Address of register. Refer to p. 60 of the datasheet. First byte always has above format. n n Sent Later Bit 7 – Set to 0 for register access. Bit 6 – Read/write control. Bits 5: 0 – Address of register. P. 60 of datasheet. Followed by data specific to register being accessed. 9/18/2021 EECS 150 Spring 2008 12

CC 2420 -specific SPI (2): Writing to Configuration Reg. Sent First Byte Number Sent Later 1 2 -3 Sent on SI address byte, described above 16 bits of data to be written to register Received on SO status byte 16’b. X n First byte followed by 2 bytes of configuration data. n n Data on SO invalid here. Transceiver replies when first byte is sent out with status byte. n n 9/18/2021 True for all SPI accesses. Not necessary to inspect, but can be helpful for debugging! EECS 150 Spring 2008 13

CC 2420 -specific SPI (3): Issuing Command Strobes Byte Number 1 n n n Sent on SI address byte, described above Received on SO status byte One byte only. Nothing follows. Address sent indicates the command strobe being issued. Note that 0 x 00 is NO OP. This is useful for explicitly retrieving status byte. 9/18/2021 EECS 150 Spring 2008 14

CC 2420 -specific SPI (4): Saving to TX FIFO Sent First Byte Number 1 Sent on SI Received on SO n n n 9/18/2021 Sent Later 2 to n address byte, described above data bytes to be transmitted status byte After first byte, send n bytes of data to transmit over wireless. SPI session only ends when CS_ is pulled high. CC 2420 replies with a new status byte with each byte that’s saved to FIFO. EECS 150 Spring 2008 15

CC 2420 -specific SPI (5): Receive from RX FIFO Received First Byte Number 1 Sent on SI Received on SO n n n Received Later 2 to n address byte, described above status byte 8’b. X data from the RX FIFO After first byte, send a n bytes of “don’t care” in order to receive data. During first byte, CC 2420 replies with status. Subsequent bytes are data saved in FIFO. Must be careful not to request data from empty FIFO! SPI session only ends when CS_ is pulled high. Reading from a configuration register is the same. 9/18/2021 EECS 150 Spring 2008 16

Configuration Registers Register Address Bit(s) of Interest Purpose MDMCTRL 0 0 x 11 11 Turn off automatic address recognition. You must set bit 11 to 1’b 0. FSCTRL 0 x 18 9: 0 Channel changing. IOCFG 0 0 x 1 C 6: 0 Changes the threshold of number of bytes in RX FIFO before FIFOP goes high. Defaults to 64. You may want to change this value. 9/18/2021 EECS 150 Spring 2008 17

Command Strobe Registers Register Address Purpose SNOP 0 x 00 No operation. SXOSCON 0 x 01 Turns on the crystal oscillator and will be used as part of the initialization process. SRXON 0 x 03 Moves the CC 2420 into the receive state and will be used as part of the initialization and channel changing process. STXON 0 x 04 Instructs the CC 2420 to transmit the data contained in the TX FIFO. SRFOFF 0 x 06 Turns off RX/TX and frequency synthesizer and will be used as part of channel changing. SFLUSHRX 0 x 08 Flushes the RX FIFO. This command will be used a lot! 9/18/2021 EECS 150 Spring 2008 18

TX/RX FIFO Registers Register Address Purpose TXFIFO 0 x 3 E For saving bytes to transmit into the TX FIFO. You must not write data to the FIFO while a transmission is in progress. RXFIFO 0 x 3 F For retrieving bytes from the RX FIFO. 9/18/2021 EECS 150 Spring 2008 19

Initialization 9/18/2021 EECS 150 Spring 2008 20

Transmit 9/18/2021 EECS 150 Spring 2008 21

Transmit(2) n CC 2420 needs 12 symbol periods to move into RX_SFD_SEARCH state after transmit done or SRXON. n n 9/18/2021 1 symbol period = 16 us. Without enforcing wait, aggressive user of your Transceiver module will cause CC 2420 to never receive data from air. EECS 150 Spring 2008 22

CCA n n n 9/18/2021 If you don’t follow CCA we will dock MAJOR points If CCA isn’t high, you must wait a RANDOM AMOUNT OF TIME CCA may also not go high if you have buffer overflow. FIFOP & !FIFO EECS 150 Spring 2008 23

Receive (1) 9/18/2021 EECS 150 Spring 2008 24

Receive (2) n n n You must be able to receive while the random CCA wait time is expiring! Packets are only received after CC 2420 has spent 12 symbol periods in receive mode. There must be wait time between transmissions. n 9/18/2021 Allows the transceiver to look for and receive data. EECS 150 Spring 2008 25

Receive(3) n Refers to 2 things: 1. 2. 9/18/2021 CC 2420 is constantly receiving and saving data into RX FIFO as long as it’s not transmitting. Look at CC 2420 internal FSM on p. 43. You have to “receive” data from RX FIFO, filter it, then save wanted data into SPIFifo. EECS 150 Spring 2008 26

Design Structure (1) n Transceiver – Highest level block. 32 -bit input/output, channel changing, addressing. n SPI Abstraction – Takes care of details of CC 2420 SPI interface. Arbitrates between TX/RX. n 9/18/2021 SPI (provided) – Handles details of interface timing. EECS 150 Spring 2008 27

Design Structure (2) n High level FSM behavior n Upon receiving a request to transmit, load TX FIFO, but wait till CCA clear to send n If CCA not clear, check if RX FIFO has something to recieve n n 9/18/2021 If data in RX FIFO, read data then check CCA again but do not assert ready until you have transmitted the last piece of data If CCA is clear, transmit return to ready state EECS 150 Spring 2008 28

Design Structure (3) n High level FSM behavior (continued) n 9/18/2021 Hint: One implementation of the overall FSM includes a state for initialization, a ready state, 2 CCA wait states, 2 TX states (load/send) and an RX state. Each of these states engages one of the FSMs presented on the previous slides. EECS 150 Spring 2008 29

Packet Format MPDU Preamble SFD Length Source Dest. Payload Frame Check Sequence (CRC) 4 bytes 1 byte 32 bytes 0 x 7 A ? ? ? Design Review Question! sender’s addr. recipient’s addr. or 0 x. FF For broadcast 0 x 00 n On transmit, 0 x 00. On receive, bit 7 of the 2 nd byte is 1 when CRC ok, 0 otherwise. On transmit, only fill TX FIFO starting with length byte. n n 9/18/2021 data Preamble & SFD automatically appended. Transmit all zeros for CRC. CC 2420 will replace. EECS 150 Spring 2008 30

Channel & Addresses n There are 16 channels. n n n Your group will be assigned a channel. You must be able to change channels without reset! DO NOT USE ANOTHER CHANNEL BESIDES YOUR OWN n n 9/18/2021 This is a big class and we need to be able to partition the signal space! Address are 8 -bits wide 256 addresses. Zero is unused. 0 x. FF is reserved for broadcast. EECS 150 Spring 2008 31

Interference & Debugging n Roughly 2 -3 groups per channel. Each group in a particular lab has distinct channel. n n n Can pick up 802. 11 packets sometimes. n n 9/18/2021 Can also pick up data on neighboring channel. Very first goal is robust channel changing during initialization. Your module must recover gracefully. Your project interferes with Wi-Fi & vice versa. EECS 150 Spring 2008 32

Handshaking: In. Request/Invalid n n 9/18/2021 SPI uses a variation of this. You may want to use this internally. EECS 150 Spring 2008 33

Handshaking: Ready/Start n Transceiver uses this interface for input & output. 9/18/2021 EECS 150 Spring 2008 34

Design Structure (4) n n 9/18/2021 When you receive a START signal, do not assert READY until you have issued the command to actually transmit the value you have loaded into the TX FIFO Upon receiving a START signal, store the input into the TX FIFO, but wait for CCA to be clear before transmitting EECS 150 Spring 2008 35

Debugging Tools n n Chipscope! We will be releasing some debugging utilities. n n 9/18/2021 Packet sniffer. Packet counter (The TA Solution does this) EECS 150 Spring 2008 36

Get Started! n n 9/18/2021 READ THE DATASHEET Obey our CCA rules EECS 150 Spring 2008 37

Danger! n Don’t become complacent because you’ve *been* finishing checkpoints early n Expect each checkpoint to be at least twice as difficult as the last. n n 9/18/2021 1>>2>>>>3>>>>4! Get started early and get ahead. EECS 150 Spring 2008 38

Checkpoint 2. 5 n 9/18/2021 Complete UI: EECS 150 Spring 2008 39

Checkpoint 2. 5 n Four Port Arbiter: SDRAM Controller Wireless Out CP 3 CP 4 Wireless Channel DCT/ Huffman Wireless In Wireless Rec. Proc. SDRAM Arbiter Wireless Send Proc. VD Proc. Subsampler Camera 9/18/2021 VE Proc. PIP Proc. Display EECS 150 Spring 2008 40

Checkpoint 2. 5 n n Check the website regularly for full the updated full spec. It makes sense to start this as soon as you finish CP 3 since you will have to do it anyway n n Extra credit incentivizes it more Any questions?