EECS 150 Intro CAD Tools EECS 150 Spring

EECS 150 Intro. & CAD Tools EECS 150 Spring 2006 Lab Lecture #1 David Lin 1/20/2006 EECS 150 Lab Lecture #1 1

Today (1) n EECS 150 Intro. n n n 1/20/2006 Labs & Lab Lecture Lab Policies Computers Webcast Website & Newsgroup Cardkeys EECS 150 Lab Lecture #1 2

Today (2) n Lab #1 n n n A Quick Introduction to CAD Verilog Testing & Verification Ca. Linx 2 CAD Tool Demo n n 1/20/2006 Project Navigator (& Synplify) Model. Sim EECS 150 Lab Lecture #1 3

Labs & Lab Lecture (1) n Watching the slides. n n Ask Questions! n n n 1/20/2006 Projector. Plasma Screen. The LCD TVs (Channel 21), audio included. If anything is unclear, please ask. Otherwise, the labs are impossible. Try to read the labs ahead of time. EECS 150 Lab Lecture #1 4

Labs & Lab Lecture (2) n n Lab lecture slides are posted early on course schedule page. Lab ZIP file. n n The assignment. n n n 1/20/2006 Contains verilog, bit-files, etc… Also contains the lab assignment. Password protected. Use login posted on white board. Personal accounts will be created later. Read & understand it ahead of time. Do it, recording answers as needed. Get checked off. EECS 150 Lab Lecture #1 5

Labs & Lab Lecture (3) n Checkoff n n n 1/20/2006 Answer any questions on the lab. Prepare any requested demos. Write down the number of hours spent (does not affect your grade). A TA will sign off that you did the lab. You must get checked off by the first 10 minutes (xx: 20) of YOUR next lab. No late credit! EECS 150 Lab Lecture #1 6

Labs & Lab Lecture (4) n Solutions n 1/20/2006 We will discuss the solution in the lab lecture after the labs. EECS 150 Lab Lecture #1 7

Lab Partners (1) n Partners n n n 1/20/2006 Labs #1 -#3 will be done alone. Labs #4 -#5 will be done in partners. But we encourage you to work with others starting from lab #1! EECS 150 Lab Lecture #1 8

Lab Partners (2) n The project will be done in groups of 2. Find a partner you trust. Start thinking about it now. n They must be in your lab section. You can switch, if necessary. n 1/20/2006 EECS 150 Lab Lecture #1 9

Lab Policies (1) n Lab Policy Enforcement n Suspend your account. n n Withhold your grades. Treat this lab with care. n 1/20/2006 Temporary for minor infractions. Permanently for major problems, this makes it REALLY hard to pass the class. You’ll be living here. EECS 150 Lab Lecture #1 10

Lab Policies (2) n Food & Drink n n Trash n n n 1/20/2006 Nowhere near the computers. You may eat at the small white tables. CLEAN UP AFTER YOURSELVES! Trash goes in the white/gray bins. Recycling in the blue bins. CLEAN UP AFTER YOURSELVES! EECS 150 Lab Lecture #1 11

Lab Policies (3) n Computer Usage n n n Other Coursework n n 1/20/2006 No CS 152 this semester. EE 24 will be in here sometimes. EECS 150 has priority, but be courteous! Feel free to work in here. EECS 150 has priority. EECS 150 Lab Lecture #1 12

Computers (1) n Computer Logins n n 1/20/2006 Account forms will be handed out during your first lab. Change your password once you get your forms. EECS 150 Lab Lecture #1 13

Computers (2) n Printing n n n 1/20/2006 There are 3 printers: A, B, and C. Computers print to nearest printer. We have a finite amount of paper, so print double sided!!! EECS 150 Lab Lecture #1 14

Computers (3) n Storage n U: is your permanent storage. n n n C: users<your username> is local storage. n n 1/20/2006 Available from all computers. Very slow, too slow to use for temp files. DELETED WHEN YOU LOG OFF, along with desktop and all your settings! Copy files back to U: drive or lose it. EECS 150 Lab Lecture #1 15

Webcast n Lab lecture will usually be “webcast, ” but not live. n n ATTEND LAB LECTURE! n n 1/20/2006 Slides will be posted in advance. If you do not attend lab lecture, you will have serious problems finishing lab/project. Webcast is not guaranteed. EECS 150 Lab Lecture #1 16

Cardkeys n Cardkeys are NOT ACTIVE. n n n Cardkey responsibility. n 1/20/2006 For now TAs will let people in. Cardkeys will be activated soon. We’ll let you know when. Don’t open the door for people who are not in CS 150. EECS 150 Lab Lecture #1 17

Website & Newsgroup (1) n The Website n n The Newsgroup n n n 1/20/2006 http: //www-inst. eecs. berkeley. edu/~cs 150/. Check it every day. We assume you’ve seen news after 48 hrs! Assignments, labs, bug updates, etc. ucb. class. cs 150. Staff will use Google Groups. Great for posting lab and HW questions. Don’t ask a question over e-mail if it’s appropriate for newsgroup. We may ignore your e-mail. EECS 150 Lab Lecture #1 18

Questions n n n n 1/20/2006 Labs & Lab Lecture Lab Policies Computers Web-cast Cardkeys Website & Newsgroup Anything Administrative EECS 150 Lab Lecture #1 19

Quick Introduction to CAD (1) n CAD = Computer Aided Design n What’s the point? Source: Keutzer, EE 244 1/20/2006 EECS 150 Lab Lecture #1 20

Quick Introduction to CAD (2) n CAD Tools n n CAD Tool Flow n 1/20/2006 Synplify Pro. Xilinx Map & PAR Tools. Model. Sim. The tools and the order in which they are applied to a given design. EECS 150 Lab Lecture #1 21

Quick Introduction to CAD (3) 1/20/2006 EECS 150 Lab Lecture #1 22

Quick Introduction to CAD (4) Sketch on Napkin assign Out = Q ^ In; always @ (posedge Clock) begin if (Reset) Q <= 1’b 0; else Q <= In; end Verilog 1/20/2006 EECS 150 Lab Lecture #1 Placed and Routed Design 23

Quick Introduction to CAD (5) n Steps to build a circuit n n n n 1/20/2006 Design the circuit (on paper). Write Verilog in Notepad. Simulate using Model. Sim. Fix the bugs. Re-simulate using Model. Sim. Synthesize. Program the board and cross your fingers. EECS 150 Lab Lecture #1 24

Verilog (1) n What’s an HDL? n n n NOT A PROGRAM n n 1/20/2006 Textual description of a circuit. Human and machine readable. Hierarchical. Meaningful naming. Describe what the circuit IS. Not what is DOES. EECS 150 Lab Lecture #1 25

Verilog (2) Digital Design Productivity, in Gates/Week Source: Data. Quest 1/20/2006 Behavioral HDL 2 K-10 K RTL HDL 1 K-2 K Gates 100 -200 Transistors 10 -20 EECS 150 Lab Lecture #1 26

Testing & Verification (1) n Develop a “Testbench” n n A non-synthesized simple verilog module. Drive inputs. n n Check outputs. Coverage is Key! n 1/20/2006 Random Test Vectors. Targeted Test Vectors <- Preferred. How many potential problems were tested? EECS 150 Lab Lecture #1 27

Testing & Verification (2) Test Bench generates inputs Test Bench outputs CUT* CUT *Circuit Under Test outputs Test Bench observes outputs prints text messages 1/20/2006 EECS 150 Lab Lecture #1 28

Testing & Verification (3) n Model. Sim does “Functional Simulation”. n n n Xilinx PAR Tools Know More. n n 1/20/2006 Great for debugging! Does not account for timing. After place and route, can extract timing. It is possible to feed timing into Model. Sim. This produces a very accurate simulation. Great for checking reliability and efficiency. EECS 150 Lab Lecture #1 29

Testing & Verification (4) n Hardware Verification n n We skip this. n n 1/20/2006 A long slow process. We prefer careful simulation earlier on. Bugs found here cost MILLIONS to fix. Does it LOOK like it works properly? Close enough… EECS 150 Lab Lecture #1 30

A Little Advice n Do the Prelab. n n n Take this lab seriously. n n 1/20/2006 Read the online tool tutorials. Otherwise this lab is very long. We know its long and boring. You’ll need to know all this by heart to pass this class with your sanity intact. EECS 150 Lab Lecture #1 31

Ca. Linx 2 Board Power Switch SW 1 -3, 5 LEDs SW 10 SW 9 FPGA Must be OFF Indicates Connection 1/20/2006 EECS 150 Lab Lecture #1 32

Using the CAD Tools n Read the Tutorials. n http: //inst. eecs. berkeley. edu/~cs 150/ sp 06/Documents. php n n Manage Your Files. n n n 1/20/2006 There are tutorials on EVERY CAD TOOL YOU NEED. Remember to copy back to U: . Clean Xilinx projects before saving. Please ask questions. EECS 150 Lab Lecture #1 33