A 77 79 GHz Doppler Radar Transceiver in

Outline • Motivation and applications of Doppler radar • Transceiver architecture and implementation challenges

Doppler Radar Review • Track range and velocity of a target without transmitted amplitude

Automotive Radar Applications • Automotive applications of Doppler radar < 1 part/billion sensitivity 150

Implementation of the Transceiver • • Single die for receiver and transmitter Tuned clock

Implementation of the Transceiver VCO supply Complete power and bias isolation LNA supply Digital

Low-noise Amplifier • 3 -stage design, add R 1 to de-Q the final stage.

Clock Buffer Design • Cascode topology is chosen for the clock buffer – high

Layout for Isolation & Bias Distribution • Layout methodology systematically addresses: – – –

Top Level Layout 0. 9 mm 1. 3 mm © Sean©Nicolson, BCTM 2006 Sean

Fabrication Technology • Two technologies with identical BEOL – w. E = 0. 13

Transmitter Output Power • Transmitter POUT vs. LO and T (230/300 GHz f. T/f.

Optimal Biasing for Si. Ge HBT PAs • Si. Ge HBT power amplifier PAE,

Receiver Conversion Gain • Peak conversion gain of 40 d. B, -3 d. B

Receiver Conversion Gain • IP 1 d. B of -35 d. Bm and OP

LNA Input Match • S 11 better than -15 d. B from 81 GHz

Receiver Noise Figure @ 1 GHz IF • JOPT is constant versus temperature bias

Receiver Noise Figure versus IF • Maximum NF of 4. 7 d. B at

Doppler Radar Experimental Setup 30 Hz DC block Bias IA ACL = 40 d.

Doppler Radar Experimental Setup © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Doppler Radar Experimental Setup > 40 cm of 110 GHz coaxial cable © Sean©Nicolson,

Example Doppler Signal • 55 Hz Doppler signal (target moving at 0. 75 km/h)

Doppler Radar Video • Human target walking forward & backward at varying speed ©

Comparison To Other Work • This work: bottom row © Sean©Nicolson, BCTM 2006 Sean

Conclusions • First single-chip silicon 82 GHz direct conversion transceiver – Fundamental VCO –

Acknowledgements • K. Yau for help with measurements • STMicroelectronics for fabrication of circuits

Slides: 28

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A 77 -79 GHz Doppler Radar Transceiver in Silicon Sean T. Nicolson 1, Pascal Chevalier 2, Alain Chantre 2, Bernard Sautreuil 2, & Sorin P. Voinigescu 1 1) Edward S. Rogers, Sr. Dept. of Electrical & Comp. Eng. , University of Toronto, ON M 5 S 3 G 4, Canada 2) STMicroelectronics, 850 rue Jean Monnet, F-38926 Crolles, France © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Outline • Motivation and applications of Doppler radar • Transceiver architecture and implementation challenges • Circuit design and layout (top level & circuits blocks) • Fabrication technology and measurement results • Detection of the Doppler shift © Sean Nicolson, BCTM 2006 © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Doppler Radar Review • Track range and velocity of a target without transmitted amplitude info Doppler shift carrier (f ) C hostile channel transceiver round trip delay (t) Target range: Target velocity: © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007 f. C ± Df moving target (v) reflected signal

Automotive Radar Applications • Automotive applications of Doppler radar < 1 part/billion sensitivity 150 -200 m Dv < 1 km/h c = 3× 108 v = 1 km/h f. C = 77 GHz • Transceiver requirements: – Long range, high PTX (not CMOS) – On-chip DSP (need CMOS) – low cost, single chip (many per car) – Low area, low power (phased arrays) • Si. Ge Bi. CMOS, direct conversion © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007 Df = 70 Hz

Implementation of the Transceiver • • Single die for receiver and transmitter Tuned clock tree used to distribute VCO signal Frequency division at 77 GHz using a static divider © Sean BCTM 2006 ©Nicolson, Sean 2007 All circuit blocks use < Nicolson, 2. 5 V supply (except divider

Implementation of the Transceiver VCO supply Complete power and bias isolation LNA supply Digital supply • • Single die for receiver and transmitter Tuned clock tree used to distribute VCO signal Frequency division at 77 GHz using a static divider © Sean BCTM 2006 ©Nicolson, Sean 2007 All circuit blocks use < Nicolson, 2. 5 V supply (except divider

Low-noise Amplifier • 3 -stage design, add R 1 to de-Q the final stage. 250 mm 1 p. F decoupling caps • Noise & Z matching inc. CPAD [Nicolson et al. , CSICS 2006] BCTMin 2006 • All circuit blocks© Sean discussed [Nicolson et al. , IMS ©Nicolson, Sean Nicolson, 2007

Clock Buffer Design • Cascode topology is chosen for the clock buffer – high reverse isolation (i. e. low S 12) – Broadband, low gain (degeneration and resistive loading) matching interface • Parameterized design of fixed size buffer to variable size load – Q 1, Q 2, LC, and LE are fixed © Sean 2006 – R 1/R 2 chosen for biasing, RBCTM ©Nicolson, Sean Nicolson, 1//R 2007 2 chosen to set Q

Layout for Isolation & Bias Distribution • Layout methodology systematically addresses: – – – Isolation of circuit blocks High-C, low-R, low-L power, ground & bias planes N-well and p-sub contacts for isolation in the substrate © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Top Level Layout 0. 9 mm 1. 3 mm © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Fabrication Technology • Two technologies with identical BEOL – w. E = 0. 13 mm with 170/200 GHz f. T/f. MAX Technology info in: [P. Chevalier et al. , – w. E = 0. 13 mm with 230/290 GHz f. T/f. MAX BCTM 2005] © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Transmitter Output Power • Transmitter POUT vs. LO and T (230/300 GHz f. T/f. MAX process) © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Optimal Biasing for Si. Ge HBT PAs • Si. Ge HBT power amplifier PAE, PSAT, and P 1 d. B vs. bias – All reach a maximum at the same current density 1. 8 V 1. 5 V © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Receiver Conversion Gain • Peak conversion gain of 40 d. B, -3 d. B bandwidth is 10 GHz Conversion Gain [d. B] 83 GHz LO 78 GHz LO 81 GHz LO © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Receiver Conversion Gain • IP 1 d. B of -35 d. Bm and OP 1 d. B of +3 d. Bm at 25°C, 2. 5 V supply • IP 1 d. B of -30 d. Bm and OP 1 d. B of 0 d. Bm at 100°C, 2. 5 V supply 83 GHz LO © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

LNA Input Match • S 11 better than -15 d. B from 81 GHz to 94 GHz • S 11 does not degrade significantly with current density © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Receiver Noise Figure @ 1 GHz IF • JOPT is constant versus temperature bias with const. IC • 3. 85 d. B NF at 25°C in receiver with 300 GHz f. MAX 81. 6 GHz LO HBT 3. 85 d. B © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Receiver Noise Figure versus IF • Maximum NF of 4. 7 d. B at 2. 5 GHz IF, 81. 6 GHz LO 4. 7 d. B © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Doppler Radar Experimental Setup 30 Hz DC block Bias IA ACL = 40 d. B 3 k. Hz Lo-Pass BNC cables 110 GHz probe & cap 12 d. B TX loss > 40 cm 110 GHz coax Scope 110 GHz probe & cap 15 cm 110 GHz coax 4 d. B RX loss 107 d. B channel loss horn antennae © Sean©Nicolson, BCTM 2006 Seangain Nicolson, 2007 (20 d. B each) Target 0. 25 m 2 6 m range

Example Doppler Signal • 55 Hz Doppler signal (target moving at 0. 75 km/h) © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Doppler Radar Video • Human target walking forward & backward at varying speed © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Conclusions • First single-chip silicon 82 GHz direct conversion transceiver – Fundamental VCO – Verified to operate at 100°C using 2. 5 V supply (3. 3 V for divider) Improved VCO will obtain improved performance over temperature – Static frequency divider at 82 GHz – Successfully detected a 55 Hz Doppler shift at 6 m range – 3. 9 – 4. 7 d. B noise figure with 82 GHz LO and 0. 5 – 4 GHz IF record for W-Band CMOS/Si. Ge receivers © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007

Acknowledgements • K. Yau for help with measurements • STMicroelectronics for fabrication of circuits & test structures • J. Pristupa, and E. Distefano for CAD & network support • CITO & NSERC for funding © Sean©Nicolson, BCTM 2006 Sean Nicolson, 2007