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Asynchronous Counter Operation Figure 9 --1 A 2 -bit asynchronous binary counter. www. themegallery. com

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Figure 9 --4 Propagation delays in a 3 -bit asynchronous (ripple-clocked) binary counter. www. themegallery. com

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Synchronous Counter Operation Figure 9 --11 A 2 -bit synchronous binary counter. www. themegallery. com

Figure 9 --12 Timing details for the 2 -bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal). www. themegallery. com

Figure 9 --13 Timing diagram for the counter of Figure 9 -11. www. themegallery. com

Figure 9 --14 A 3 -bit synchronous binary counter. www. themegallery. com

Figure 9 --15 Timing diagram for the counter of Figure 9 -14. www. themegallery. com

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Figure 9 --16 A 4 -bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas. www. themegallery. com

Figure 9 --17 A synchronous BCD decade counter. www. themegallery. com

Figure 9 --18 Timing diagram for the BCD decade counter (Q 0 is the LSB). www. themegallery. com

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Up/Down Synchronous Counter www. themegallery. com

Figure 9 --23 A basic 3 -bit up/down synchronous counter. www. themegallery. com

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Design of Synchronous Counters Figure 9 --27 General clocked sequential circuit. www. themegallery. com

Step 1: State Diagram Figure 9 --28 State diagram for a 3 -bit Gray code counter. www. themegallery. com

Step 2: Next-State Table www. themegallery. com

Step 3: Flip-Flop Transition Table www. themegallery. com

Step 4: Karnaugh Maps Figure 9 --29 Examples of the mapping procedure for the counter sequence represented in Table 9 -7 and Table 9 -8. www. themegallery. com

Step 5: Logic Expressions for Flip-Flop Inputs Figure 9 --30 Karnaugh maps for present-state J and K inputs. www. themegallery. com

Step 6: Counter Implementation Figure 9 --31 Three-bit Gray code counter. www. themegallery. com

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Figure 9 --35 Example 9 -6 - State diagram for a 3 -bit up/down Gray code counter. www. themegallery. com

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Cascaded Counters Figure 9 --38 Two cascaded counters (all J and K inputs are HIGH). www. themegallery. com

Figure 9 --39 Timing diagram for the cascaded counter configuration of Figure 9 -38. www. themegallery. com

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Figure 9 --43 A divide-by-100 counter using two 74 LS 160 decade counters. www. themegallery. com

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Counter Decoding Figure 9 --45 Decoding of state 6 (110). www. themegallery. com

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Counter Applications : Digital Clock Figure 9 --51 Simplified logic diagram for a 12 -hour digital clock. Logic details using specific devices are shown in Figures 9 -52 and 9 -53. www. themegallery. com

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Figure 9 --53 Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the rightmost bit is the LSB. www. themegallery. com

Counter Applications : Automobile Parking Control Figure 9 --54 Functional block diagram for parking garage control. www. themegallery. com

Figure 9 --55 Logic diagram for modulus-100 up/down counter for automobile parking control. www. themegallery. com

Counter Applications : Parallel-to-Serial Data Conversion (Multiplexing) Figure 9 --56 Parallel-to-serial data conversion logic. www. themegallery. com

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Application Figure 9 --66 Traffic light control system block diagram and light sequence. www. themegallery. com

Figure 9 --67 Block diagram of the sequential logic. www. themegallery. com

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Figure 9 --69 Sequential logic. www. themegallery. com

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Figure 9 --70 www. themegallery. com

Figure 9 --71 www. themegallery. com

Figure 9 --72 www. themegallery. com

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