Lecture 26 Gate delays MOS logic Today Gate

Lecture #26 Gate delays, MOS logic Today: • Gate delays • Another look at CMOS logic transistors 11/1/2004 EE 42 fall 2004 lecture 26 1

Controlled Switch Model of Inverter VOUT VDD = 3 V VIN =3 V RN V-SS = 0 V Output when: + VOUT - RP + VOUT V-SS = 0 V 11/1/2004 3 0 VDD = 3 V VIN =0 V VIN jumps from 3 V to 0 V - VIN jumps from 0 V to 3 V t. D t What is the gate delay t. D for this simple inverter? If we define t. D as the time to go halfway to the asymtotic limit, t. D = 0. 69 RC. To get equal delays we will need to set RP = RN. EE 42 fall 2004 lecture 26 2

Simple model for logic delays (slide 2 again) We model actual logic gate as an ideal logic gate fed by an RC network which represents the dominant R and C in the gate. R Ideal Logic gate VX C v OUT ( t ) Ideal Logic gate etc. Model of Actual Logic Gate v. IN VX 11/1/2004 v. OUT This model is very close to real physics: the transistors are inherently extremely fast, but are slowed by the need to charge up (or discharge) the capacitance at the various nodes. t t. D = 0. 69 RC EE 42 fall 2004 lecture 26 3

NMOS and PMOS use the same set of input signals CMOS Logic Gate VDD PMOS only in pull-up PMOS conduct when input is low A B PMOS do not conduct when A +(BC) C VOUT B A NMOS only in pull-down NMOS conduct when input is high. NMOS conduct for A + (BC) C 11/1/2004 Logic is Complementary and produces F = A + (BC) EE 42 fall 2004 lecture 26 4

CMOS Logic Gate: Example Inputs VDD A=0 B=0 C=0 PMOS all conduct A Output is High B C VOUT B = VDD NMOS do not conduct A C 11/1/2004 Logic is Complementary and produces F = 1 EE 42 fall 2004 lecture 26 5

CMOS Logic Gate: Example Inputs VDD A=0 B=1 C=1 PMOS A conducts; B and C Open A Output is High B C VOUT B =0 NMOS B and C conduct; A open A C 11/1/2004 Logic is Complementary and produces F = 0 EE 42 fall 2004 lecture 26 6

Switched Equivalent Resistance Network V VDD DD RU A A RU RU B C VOUT C B Switches close when input is low. VOUT RD B A RD A C 11/1/2004 B RD Switches close when input is high. C EE 42 fall 2004 lecture 26 7

Logic Gate Propagation Delay: Initial State VDD The initial state depends on the old (previous) inputs. RU A RU RU C B VOUT RD RD B A The equivalent resistance of the pull-down or pullup network for the transient phase depends on the new (present) input state. RD Example: A=0, B=0, C=0 for a long time. These inputs provided a path to VDD for a long time and the capacitor has charged up to VDD = 5 V. COUT = 50 f. F C 11/1/2004 EE 42 fall 2004 lecture 26 8

Logic Gate Propagation Delay: Transient VDD At t=0, B and C switch from low to high (VDD) and A remains low. RU A RU RU C B VOUT RD RD And opens a path from VOUT to GND COUT discharges through the pull-down resistance of gates B and C in series. B A RD C 11/1/2004 This breaks the path from VOUT to VDD COUT = 50 f. F Dt = 0. 69(RDB+RDC)COUT = 0. 69(20 k. W)(50 f. F) = 690 ps The propagation delay is two times longer than that for the inverter! EE 42 fall 2004 lecture 26 9

Logic Gate: Worst Case Scenarios VDD What combination of previous and present logic inputs will make the Pull-Up the fastest? RU A RU RU C B VOUT RD RD B A RD C 11/1/2004 What combination of previous and present logic inputs will make the Pull-Up the slowest? What combination of previous and present logic inputs will make the Pull-Down the fastest? COUT = 50 f. F What combination of previous and present logic inputs will make the Pull-Down the slowest? EE 42 fall 2004 lecture 26 Fastest overall? Slowest overall? 10

MOS transistors • The heart of digital logic is the MOS transistor, both NMOS and PMOS • In the next couple of lectures, we will learn more about how CMOS logic works at the circuit level, • starting with a review of the NMOS transistor 11/1/2004 EE 42 fall 2004 lecture 26 11

NMOS TRANSISTOR STRUCTURE “Metal” gate (Al or Si) • NMOS = N-channel Metal Oxide Silicon Transistor gate tor sula oxide in n n icon il P-type S • An insulated gate is placed above the silicon • Its purpose is to control the current between n-type regions (by inducing a “channel” of electrons when a positive V is applied). 11/1/2004 EE 42 fall 2004 lecture 26 12

MOS TRANSISTOR STRUCTURE DEVICE IN CROSS-SECTION “Metal” “Oxide” “Semiconductor” G “Metal” gate (Al or Si) S n gate oxide insulator D n P • The “gate” electrode is just a conductor to act as the capacitor top plate • The lower “body” electrode is silicon with almost no electrons present (essentially an insulator) • Thus no current can flow between the D and S electrodes which contact the silicon 11/1/2004 EE 42 fall 2004 lecture 26 13

MOS TRANSISTOR STRUCTURE DEVICE with + Gate Voltage S + 5 V n G “Metal” gate (Al or Si) ++++++ _ _ _oxide _ _ _insulator ______ D n P • Here the 5 V across the capacitor induces + charge on the gate and – charge on the surface of the semiconductor, according to Q=CV. • The charge in the semiconductor is really just free electrons which can carry current (just like the electrons in a metal can carry current). • Thus by applying a voltage to the gate we have provided a conduction path for current if a voltage is applied from D to S. 11/1/2004 EE 42 fall 2004 lecture 26 14

MOS Transistor as a controlled switch VGS + S i G i. D VGS >> VT D VGS > VT oxide Si tox + VDS i. D Zero if VGS is small V DS But the device is not fundamentally ON/OFF. As VGS increases, the switch resistance decreases (slope becomes steeper). Thus we have a “family of I-V curves” which describe the current into D as a function of both VDS and VGS 11/1/2004 EE 42 fall 2004 lecture 26 15

Three-Terminal Device Graphs ID (m. A) ID 3 -Terminal Device G VGS D 10 ID versus VDS for VGS = 2 V. + S Concept of 3 -Terminal Device Graphs: 1 2 VDS (V) We set a voltage (or current) at one set of terminals (here we will apply a fixed VGS of 2 V) and conceptually draw a box around the device with only two terminals emerging So we can now plot the two-terminal characteristic (here ID versus VDS). 11/1/2004 EE 42 fall 2004 lecture 26 16

Three-Terminal Parametric Graphs ID 3 -Terminal Device G VGS ID (m. A) D 10 + - VGS = 3 VGS = 2 VGS = 1 S Concept of 3 -Terminal Parametric Graphs: We set a voltage (or current) at one set of terminals (here we will apply a fixed VGS) 1 2 VDS (V) and conceptually draw a box around the device with only two terminals emerging so we can again plot the two-terminal characteristic (here ID versus VDS). But we can do this for a variety of values of VGS with the result that we get a family curves. 11/1/2004 EE 42 fallof 2004 lecture 26 17

NMOS I vs V Characteristics Example of experimental I-V characteristics. (You can do in the 43 Lab) ID S VGS + G i. D D VDS + VGS = 2 VGS = 1. 5 VGS = 1 VGS = 0 VDS For low gate voltages, no drain current flows. As VGS is increased above threshold, e. g. 1 V, the nonlinear “saturating” I-V curve is obtained. Increasing VGS causes ID to increase, as the family of curves indicates. 11/1/2004 EE 42 fall 2004 lecture 26 18

The Family of ID vs VGS Curves For short-channel devices used in digital logic, the ID vs VDS curves are decidedly nonlinear! Curves which start out as simple linear resistors saturate as shown on this and the previous slide. We can approximate the I-V characteristics as two straight lines. a) the linear “resistance” region at low VDS and b) the saturation region (almost horizontal) at larger VDS. 11/1/2004 ID(m. A) 1. 25 4 3 2 1 0. 75 0. 5 0 EE 42 fall 2004 lecture 26 0. 5 VDS 19

NMOS Summary ID ID G D IDS ID for VGS = maximum (VDD) N Ch S If VGS = 0. The circuit symbol VDS VDD D A value for RDN is chosen to give the correct timing delay. RDN G S Electrical Model 11/1/2004 EE 42 fall 2004 lecture 26 20

Remember the Role of the Switch VIN The NMOS transistor conducts the charge out of the capacitor to ground when its input (VGS) is high (VDD). VDD = 3 V We cover up the non-useful parts of the circuit for simplicity. G D =3 V + The capacitor was initially at 3 V VOUT (VDD), and goes toward zero. We RN define one stage delay by the time for S - V = V to reach 1. 5 V (V /2). OUT DS DD - SS = 0 V V ID Now lets draw the I-V VGS = VDD characteristics of the NMOS IDS When VGS jumps to VDD, the current jumps from zero to this value. VGS = 0 11/1/2004 VDD/2 VDD As the capacitor discharges, V decreases and the current follows the IDS vs VDS curve. As a first approximation we will EE 42 fall assume 2004 lecturethat 26 l=0 21

Computing the stage delay The stage delay is the time for VOUT to decrease from VDD to VDD /2. + VIN =3 V - G D RN - C + VOUT - S ID VGS = VDD IDS As V goes from VDD to VDD /2, the average current IAV IDS( 1+l. X(3/4)VDD) ( IDS if l is close to zero; consider this case first). We integrate the capacitor equation to find the time: =CVDD/2 IDS for l = 0 VGS = 0 11/1/2004 The capacitor is initially charged to 3 V, and we want to see how long it takes to reach 1. 5 V. That is the delay. VDD/2 VDD VDS As the capacitor discharges, V decreases and the current follows the IDS vs VDS curve. EE 42 fall 2004 lecture 26 22

Computing the stage delay (for l 0) The stage delay t is the time for VOUT to decrease from VDD to VDD /2. + VIN =3 V - G D RN - C + V OUT - S ID IDS Thus t = CVDD/2 IDS for l = 0 VGS = VDD We would compute t = 0. 69 RC = 0. 69 (3 VDD/4 IDS )C That is t = 0. 52 CVDD/IDS which is only 4% larger than the value we found by doing the actual integration. VGS = 0 11/1/2004 VDD/2 Now suppose we had instead assumed a resistance which averaged VDD/IDS and VDD/2 IDS , that is 3 VDD/4 IDS , shown as the blue line in the figure below. VDD VDS Here we approximate l = 0 so the slope is zero EE 42 fall 2004 lecture 26 23

Computing the stage delay (for l >0) We found by integration that + VIN =3 V - G D RN - + C VOUT Since IAV IDS( 1+l. X(3/4)VDD) we have t =0. 5 C VDD / IDS( 1+l. X(3/4)VDD). Now lets compare with the value we would get using an averaged-value resistor (blue line below) - S As VOUT goes from VDD to VDD /2, the average resistance is (3/4) VDD / IDS( 1+l. X(3/4)VDD) thus our time constant (0. 69 RC) equals ID VGS = VDD IDS Again, this is only 4% different from the answer obtained by direct integration As the capacitor discharges, VOUT decreases and the current follows the IDS vs VDS curve. VGS = 0 11/1/2004 t=0. 69 C (3/4) VDD / IDS( 1+l. X(3/4)VDD) = 0. 52 C VDD / IDS ( 1+l. X(3/4)VDD) VDD/2 VDD VDS EE 42 fall 2004 lecture 26 24

Computing the stage delay - Summary + VIN =3 V - G D RN - + C VOUT - S During the discharge of C through the NMOS transistor, we have shown that we can compute the stage delay t by using the switch model with an effective resistance RDN = (3/4) VDD / IDS( 1+l. X(3/4)VDD) Thus we can compute the stage delay, 0. 69 RDNC, IDS ( 1+l. VDD) ID VGS = VDD D IDS RDN G VGS = 0 11/1/2004 VDD/2 VDD VDS S Electrical Model EE 42 fall 2004 lecture 26 25