Design and Implementation of VLSI Systems EN 1600

Design and Implementation of VLSI Systems (EN 1600) lecture 09 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson] S. Reda VLSI Design

Summary of transistor operation NMOS transistor S. Reda VLSI Design PMOS transistor

DC transfer characteristics S. Reda VLSI Design

PMOS on (linear), NMOS off • Vin = 0 S. Reda VLSI Design

PMOS on (linear), NMOS on (saturation) • Vin = 0. 2 VDD S. Reda VLSI Design

PMOS on (linear ~ sat) and NMOS (sat) • Vin = 0. 4 VDD S. Reda VLSI Design

PMOS on (sat) NMOS on (linear) • Vin = 0. 6 VDD S. Reda VLSI Design

PMOS on (off ~ linear) and NMOS on (linear) • Vin = 0. 8 VDD S. Reda VLSI Design

NMOS on (linear) and PMOS cut off • Vin = VDD S. Reda VLSI Design

Summary of voltage transfer function A B C S. Reda VLSI Design D E

Noise margins S. Reda VLSI Design

CMOS inverter noise margins desired regions of operation S. Reda VLSI Design

What is the impact of altering the PMOS width in comparison to the NMOS width on the DC char? Idsn, |Idsp| Vin 3 Vout VDD If we increase (decrease) the width of PMOS compared to NMOS for the same input voltage, a higher (lower) output voltage is obtained V out S. Reda VLSI Design V in

Impact of skewing transistor sizes on inverter noise margins Ø Increasing (decreasing) PMOS width to NMOS width increases (decreases) the low noise margin and decreases S. Reda VLSI Designthe high noise margin (increases)

Pass transistor DC characteristics Ø As the source can rise to within a threshold voltage of the gate, the output of several transistors in series is no more degraded than that of a single transistor S. Reda VLSI Design

Summary ü Ideal transistor characteristics ü Non-ideal transistor characteristics ü Inverter DC transfer characteristics § Simulation with SPICE and integration with L-Edit S. Reda VLSI Design