P 08311 FPGA Based multipurpose driver data acquisition

P 08311: FPGA Based multi-purpose driver / data acquisition system Team Member Discipline Role Andrew Fitzgerald CE Project Manager/FPGA and PC Interface Brian Pinkham EE Input Subsystem – A/D Steven Fastow CE FPGA Programming and PC Interface Murtuza Quaizar EE Schematic and Documentation Corey Van. Blarcom EE PCB Layout and Repair Sponsor: Dr. Marcin Lukowiak 1

Why? Problem ◦ Devices that record digital or analog output provide no way of generating input for a device under test. Solution ◦ Have a reconfigurable device that allows both data sampling and data generation in the digital and analog realms. 2

Basically… Waveform Generator Output: Logic Pattern Generator AND Input: AND Oscilloscope Logic Analyzer 3

High Level Customer Needs Input Capabilities Digital 12 Channels Analog Voltage 16 Channels Output Capabilities Digital 12 Channels Analog Voltage 8 Channels Analog Current 8 Channels • System • Composed of FPGA with embedded processor • Embedded processor communicates with attached host computer • 2 minute sample time • Breakout connections • Convenient storage format for recorded data 4

Project breakdown 5

Hardware Concept 6

Finished Hardware 7

8

Data Acquisitions Results: Filtering 9

Sampling Rate Results: Analog Input / Output

Voltage Drivers Results: Analog Output Gain

Current Driver Required Load Volts In (V) I out (m. A) 0. 007 0. 5 2. 11 1. 0 4. 09 1. 5 6. 06 2. 0 8. 05 2. 5 10. 05 3. 0 12. 02 3. 5 13. 97 4. 0 15. 88 4. 5 17. 73 5. 0 19. 72 4 – 20 m. A Output With 250 Ohm

Embedded Processor - UI 13

FPGA Resources used ◦ Slices Communication with embedded processor ◦ FIFO and registers 14

Final Status PCB Board Completed and Debugged Final Schematic with errors fixed Analog Filter produces a 3 d. B Cutoff at 1. 4 KHz Multiples Analog inputs channels have been tested and documented ADC and DAC work 15

Final Status Digital I/O with 4 Voltage Rails Storage in Compact Flash Portable and Variable Storage Size Common ATX 20 Pin Power Supply 16 16

Final Status – Unresolved Issues Embedded processor ◦ Does not operate fast enough to process data from the FPGA to meet specification ◦ Multiple operations drastically affect output speed Dynamic Ranges reduced ◦ Analog inputs -> 0 – 5 V ◦ Analog Voltage outputs -> -8 V – 11 V Analog filtering was reduced in designed robustness for 12 inputs 17 17

Image References Oscilloscope ◦ http: //cp. home. agilent. com/upload/cmc_upload/o scilloscope. gif Waveform Generator ◦ http: //www. em-tek. co. kr/admin/data/33250 A. JPG Logic Pattern Generator ◦ http: //www. n-denkei. com/tektronix_tds 2024. jpg Logic Analyzer ◦ http: //www. elexp. com/test/LA-100. jpg 18