P 09311 FPGA Based MultiPurpose Driver Data Acquisition
P 09311: FPGA Based Multi-Purpose Driver / Data Acquisition System Team Member Discipline Role Adam Van Fleet EE Project Manager/Documentation David Howe EE Hardware System Development Michael Doroski CE Andrew Weida CE FPGA Buffer Subsystem Programming and Digital/Analog Interfacing Bluetooth and GUI Development T. J. Antonoff CE USB Development Sponsor: Dr. Marcin Lukowiak 1
Project Description n Goal: Design and implement a functional FPGA-based interface for the multi-purpose driver/data acquisition system. The interface must allow for data acquisition via USB and Bluetooth communication interfaces. n Utility: The project is to be utilized in Robotics and ASIC testing for research at the Rochester Institute of Technology.
High Level Customer Requirements Input Capabilities Output Capabilities Digital 12 Channels Analog Voltage 16 Channels Analog Voltage 8 Channels Analog Current 8 Channels Data Transfer Capabilities Bluetooth 1. 2 kb/s minimum (100% transfer rate) USB 1. 5 Mb/s minimum (100% transfer rate) Sampling Rate 20, 000 samples/second • System • Utilizes FPGA interface. • Capable of transferring data via Bluetooth and USB communication channels. Option for Ethernet and Wireless communication channels. • Infinite sampling time desired (data streaming). • GUI displays data transfer statistics. • Text-file format for data storage. 3
Hardware Implementation ASIC or Robotics Input Windows-Based PC P 08311 DAQ Board DLP-USB 245 M USB Adapter Parani ESD 210 SK Bluetooth Dev. Kit Spartan-3 FPGA 4
Top Level Architecture Design FPGA Input Conditioning Output Subsystem USB 8 Mbps USB Data Routing Logic USB FIFO USB Cable DAQ PC Control Unit Serial Output Conditioning Input Subsystem UART Tx RS 232 200 kbps Rx Bluetooth Wireless Tx Rx Bluetooth Modules 5
Product Development Process Phase n Phase 0: Planning q Phase 1: Concept Development n Phase 2: System Level Design q Phase 3: Detailed Design § Phase 4: Testing and Refinement
Concept Summary Theory: The buffers can only empty as fast as the communication channel allows, but can load as fast as we choose. The buffer size is 216 kb. The length of time for which we can transfer data is equal to the total memory size (216 kb) available, divided by the rate the memory is filled (Input Rate – Output Rate). Therefore, if the output rate is greater than the input rate, we can transfer information for an infinitely long period of time. 7
Concept Summary (Bluetooth) The Bluetooth device can only handle theoretical bit rates of 330 kb/s, limited by baud rate, and is seeing 200 kb/s in testing. Under full load, over 6 Mb/s is required. Therefore, the BT device will not be sufficient for data transfer under full load. Input Rate (kb/s) Time (t) 199. 99 1 E+15 250 4. 32 200. 01 21600 300 2. 16 200. 1 2160 350 1. 44 201 216 400 1. 08 205 43. 2 500 0. 72 210 21. 6 1000 0. 27 220 10. 8 2000 0. 12 230 7. 2 3000 0. 077 240 5. 4 4000 0. 057 8
Concept Summary (USB) The USB system allows for an 8 Mb/s transfer rate, thus the buffer is never filled and data transfer can be streamed (infinite time length). Under full load, the maximum output rate required for streaming is 6, 724 kb/s. Input Rate (kb/s) Time (t) 0 1 E+15 2500 1 E+15 100 1 E+15 3000 1 E+15 200 1 E+15 3500 1 E+15 300 1 E+15 400 1 E+15 4500 1 E+15 5000 1 E+15 1000 1 E+15 5500 1 E+15 1500 1 E+15 6000 1 E+15 2000 1 E+15 6500 1 E+15 9
Design Summary The packet structure is broken down into: -MSB (B 7): Determines if data is Analog or Digital -B 6 to B 4: Used to reassemble data on PC side -LSB’s (B 3 to B 0): Contain the data from DAQ or PC If the top nibble is set to ‘ 1111’, the last 4 data bits determine which analog channel the data is being received from. 10
Graphical User Interface (GUI) 11
Analog I/O Testing A 3. 3 Vpp sin wave is fed to the analog inputs of the DAQ, then through the Spartan-3 FPGA. The analog outputs are as shown. It is noted that as the frequency approaches 1 k. Hz (left), the signal begins “stair-stepping”, as seen in P 08311’s work. As the frequency increases to 2 k. Hz and above (right), the stepping becomes much more apparent.
Digital I/O Testing A 1. 5 Vpp square wave is fed to the digital inputs of the DAQ, then through the Spartan-3 FPGA. The digital outputs are as shown.
Status of Design n Bluetooth System q n USB System q n In system-level debugging to achieve customer specifications. Graphical User Interface q n Meets customer specifications Meets customer display specifications Accurately depicts transfer rate and connection settings, allows for file selection. Under budget of ~$500 Schedule: 2 weeks behind schedule on USB, Bluetooth on schedule, ahead of schedule on GUI Interface. 14
Unresolved Issues Bluetooth limited by memory size Baud rate allows for 360 kb/s max. transfer rate 16 Mb additional memory requires project rework USB Transmission Errors Digital Output 2 stuck at ‘ 1’ May require a new IC chip Analog Data Transfer Signals misrouted, likely due to timing errors. 15
MSDII Project Milestones n n n n 4/03 – Concept Review 4/10 – Finalize Design, Review System Concept 4/20 – Subsystems Finalized, Begin Test & Debug 5/05 – Entire System Finalized, Begin Test & Debug 5/08 – Finalize and Submit Documentation 5/15 – Project Review 5/18 – Field Demo and Project Wrap-up
Q&A Questions?
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