P 08311 FPGA Based multipurpose driver data acquisition
P 08311: FPGA Based multi-purpose driver / data acquisition system Team Member Discipline Role Andrew Fitzgerald CE Project Manager/FPGA and PC Interface Brian Pinkham EE Input Subsystem – Digital Steven Fastow CE FPGA Programming Murtuza Quaizar EE Input Subsystem – Analog Corey Van. Blarcom EE Output Subsystem/Power Management Sponsor: Dr. Marcin Lukowiak 1
Why? Problem ◦ Devices that record digital or analog output provide no way of generating input for a device under test. Solution ◦ Have a reconfigurable device that allows both data sampling and data generation in the digital and analog realms. 2
Basically… Waveform Generator Logic Pattern Generator Oscilloscope Logic Analyzer Output: Input: 3
High Level Customer Needs Input Capabilities Digital 12 Channels Analog Voltage 16 Channels Output Capabilities Digital 12 Channels Analog Voltage 8 Channels Analog Current 8 Channels • System • Composed of FPGA with embedded processor • Embedded processor communicates with attached host computer • 2 minute sample time • Breakout connections • Convenient storage format for recorded data 4
Project breakdown 5
Hardware Concept 6
GUI Concept 7
Technical Risk Assessment POSSIBLE SHOWSTOPPERS Reaching the analog sample rate desired by our customer ◦ Simulations and prototyping Xilinx IP Cores will expire and become nonfunctional ◦ Requesting an ‘educational donation’ to RIT for the cores ◦ Exploring open cores Java API used by GUI might not communicate with embedded processor ◦ Testing with systems already connected over Ethernet Transfer rate to data storage may not be fast 8
Current Status Current customer needs are met All prototyping parts received with the exception of the USB JTAG programmer Status ◦ Communication has been established between the FPGA and the embedded processor ◦ Simulations of input and output analog hardware have been completed 9
Expense Report $199, 00 $34, 16 $38, 98 $90, 40 Virtex 4 Dev Board Prototyping Parts Basic I/O (OUTDATED) Prototyping Parts Reconfig. IC Adapters $495, 00 Prototyping Parts Basic I/O Prototyping Parts Linear Regulators USB JTAG Programmer $15, 57 $326. 89 remaining out of $1200. 00 initial budget 10
Project Schedule MSD I • Week 11 – Parts Ordered • Design Finalized MSD II • Week 1 -2 – Parts Arriving • Implement at least one full channel of analog from input to output with the FPGA • Basic communication between the PC and FPGA implemented • PCB for analog daughter board ordered • Week 3 -6 – Finished PCB Arriving • FPGA communication established with GUI on host computer • Full system prototype completed • Weeks 7 -8 • Verify design through testing • Begin team poster and technical paper • Weeks 9 -10 • Finalize documentation • Complete team poster and technical paper 11
Image References Oscilloscope ◦ http: //cp. home. agilent. com/upload/cmc_upload/o scilloscope. gif Waveform Generator ◦ http: //www. em-tek. co. kr/admin/data/33250 A. JPG Logic Pattern Generator ◦ http: //www. n-denkei. com/tektronix_tds 2024. jpg Logic Analyzer ◦ http: //www. elexp. com/test/LA-100. jpg 12
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