EECS 465 Digital Systems Lecture Notes 7 A

EECS 465: Digital Systems Lecture Notes # 7 (A) Introduction to Sequential Circuits (B) Latches and Flip-Flops (C) Counter Design SHANTANU DUTT Department of Electrical and Computer Engineering University of Illinois, Chicago Phone: (312) 355 -1314: e-mail: dutt@eecs. uic. edu URL: http: //www. eecs. uic. edu/~dutt

(A) Introduction to Sequential Circuits • Current o/p depends on the current i/p and past history of all i/ps seen by the circuit. Where the relevant past history should be representable by a finite number of classes or states Reset Light = Green O/P = 1 Light = Not red O/P = 0 No Red Encode as state=0 Light = Red O/P = 0 Red Light State Transition Diagram Encode as state = 1 Light = Not green O/P = 0 Design Problem: Output of the circuit is 1 only if it has seen a red light in the past and currently light is green.

Circuit-Level Model of a Sequential Circuit. I/p from x 0 external xn-1 point State bits of seq. ckt. Z 0 Combinational Circuit yk-1 Zm-1 y’k-1 y 0 y’ 0 Current State Memory Unit Next State Going to external world

(B) Latches and Flip-Flops Components to store bits ( latches or flip flops ) Problem: can’t store new data 0 1 1) 1 1 Cascade of inverter LD 2) 0 I/P LD 1/0 O/P A Will conduct when A=1, and open when A=0

Another storage element: NOR gates ( R-S latch ) 3) Cross coupled NOR gates ( R-S latch ) R (Reset) Q 0 Q R=0 1 S=1 0 B S (Set) Property of a NOR gate A=0 When one I/P of NOR is 0, it acts like an inverter. When one I/P is 1, then O/P=0. Different I/P conditions for R-S latch: i) R=S=0, current I/P is stored indefinitely Hold ( becomes cascade of inverters) Q

ii) R=1, S=0, when we want to store a 0 in the R-S latch. Q=0, iii) R=0, S=1, when we want to store a 1 in the latch. Q=1, iv) R=1, S=1; Forbidden inputs! Both Q = 0, : Q and its complement have the same value ! Will play havoc in the rest of the logic circuit. Transit to: R=0, S=0. R=1, S=1, 0 R=1 0 0 0 and 0. O/P oscillates. Q 0 1 1 S=1 0 both Q and 0 1 0 Oscillates between 1 and 0 when we transit from R=S=1 to R=S=0.

From R, S = 1, 1 transit to R=0, S=1 then Q, transit to 1, 0 ( correctly ) From R, S = 1, 1 transit to R=1, S=0 then Q, correctly transit to 0, 1 Two implementations for R-S latch: Cross-coupled NOR R Cross-coupled NAND R Q S S Hold State Q Hold State R=S=1 R=0, S=0 R=1, S=1 Q Forbidden I/Ps

4) The D-Latch R R 1 R-S enb D Q Latch S S 1 D=1, S=1, R=0 enb=1 Q=1, D=0, S=0, R=1 enb=1 Q=0, enb=0 R 1, S 1=0 (hold state) Clocked Latch (level-sensitive clock latch) — see terminology defined later.

5) The J-K Latch: — Proposed to get rid of the forbidden I/P problem of R-S i) J=1, K=0: (a) Let Q=1, R=0, S=0 Hold state of R-S Q=1, (b) Let Q=0, , R=0, S=1 Q=1, ii) J=0, K=1 Q=0, using a similar analysis iii) J=K=0 Hold state iv) J=K=1, suppose Q=1, =0 R=1, S=0 Q=0, =1 S=1, R=0 Q=1, =0 This type of toggling continues as long as J=K=1, and the latch is enabled ( CLK=1 below ) K Q 1 0 R CLK J R R-S 1 0 1 S Q

Latch classification with respect to response to “control signal” Terminology: Note that the terminology below applies to all types of latches: i) R-S, D, J-K, T, etc. , though the examples are given for the R-S latch. Transparent Latch: O/P responds to latch I/Ps without any enable or clock signal. R Q Symbol: R S Q S Clock or enb Clock: Fixed frequency alternating 1 and 0 signal ii) Clocked or Level-Sensitive Latch: R O/P responds to I/Ps only when enb or Q clock is at a pre-determined level (high or low — In this example, it is High) S Symbol: R S Q or CLK (high enable) R S CLK Q (low enable)

iii) Edge-Triggered Flip-Flop (FF) or simply Flip-Flop O/P will respond to I/Ps only at either: (a) the positive or rising edge of the enb/clock signal (positive Symbol: edge-triggered FF), or R Q S CLK (b) the negative or falling edge of the enb/clock signal (negative edge-triggered FF). R Q Symbol: S CLK Clock: O/P resp. period for a low-enable/clock level sensitive latch O/P response period for a positive edge-triggered FF. O/P response period for a negative edge-triggered FF O/P response period for a HIGH-enable/clock level-sensitive latch

Setup Times and Hold Time of FFs and Latches • Assume, positive edge-triggered D-FF THold relates to propagation delay of another part of circuit. D CLK TSetup relates to propagation delays of The high point of various gates in the FF. the CLK determines the positive edge’s arrival. • If negative edge-triggered TSetup THold D CLK Negative edge arrival • If D-Latch is high-level sensitive: Tsetup and Thold have to be around the negative edge of clock (more specifically, when the clock begins to go low), similar to negative edge-triggered. • If D-Latch is low-level sensitive: Tsetup and Thold have to be around the positive edge of clock, similar to positive edge-triggered.

Solutions to Race Condition Problem with Level Sensitive Latches Solution 1: Master-Slave FF: Q R 1 J 0 S K 1 R-S Latch Qm 1 P 0 1 0 R R-S S Qs 0 CLK Slave R-S is level sensitive. Master-Slave J-K is a solution to race-condition problem: Any change in Q, during CLK=0 is not propagated to P, and hence back to Q, during the same CLK=0. Any change to Q, will occur in next CLK=0 period. J K J-K M-S (O/P responds when CLK goes From 1 to 0) Q Master-Slave J-K works similar to a J-K latch: E. g. Let J=1, K=1, CLK=1 Q=1, =0 =1 , P=0 When CLK=0 Q=0, =1 Q

Solution 2: Edge-Triggered FF: D R Holds when clock goes low R 0 D=1=S Q=1, Q =D Clk=0 Q S Clk=1 D 0 Assume D=1 S D Holds D when clock goes low D Q responds to internal S signal; responds to internal R signal. CLK D When CLK is 1 D I/P is internally sampled but does not appear at the O/P. 0 R Clk=0 S D D 0 O/P appears (Q=D) Q O/P is held (changing D does not cause any change in internal signals in the FF or in its output)

Characteristic Equations of Latches/FFs The next O/P Q+ defined in terms of the current O/P Q and the I/P. (FF/Latch is the simplest possible sequential ckt. ) 1) R-S Latch— Truth Table: Values at time t S(t) R(t) Q(t) 0 0 0 1 1 1 0 0 1 1 1 Q(t)SR 00 0 0 1 1 01 0 0 11 x x Q+ = Q( t+ ) 0 Hold 1 0 Reset 0 1 Set 1 x Forbidden x 10 1 1 Q+= S+ Q (Characteristic equation)

Similarly: Characteristic Equations of 2) J-K, Q+ = Q 3) D-FF, Q+ = D 4) Toggle FF/Latch or T-FF / Latch + J. Q+ = T+Q Symbol: T Whenever I/P T is high, the FF will toggle, i. e. , Q+ = When T=0, Q+=Q. . Of course, these characteristic equations come into play only when the FF/Latch is enabled. Q

Excitation Table — Reversed Truth Table — What the inputs to FFs should be for given output transitions (Q Q+) Q 0 0 1 1 Q+ 0 1 R x 0 1 0 S 0 1 0 x J 0 1 x x K x x 1 0 T 0 1 1 0 D 0 1

— Conversion between FFs Example: J-K to D D J Logic This should behave like a D-FF. Q K CLK D Q 0 Q 1 O/P function = J 0 J=D 0 1 1 x x D D Function = K K= Map the D, Q input combination to a Q Q+ transition and then map this to J-K excitation required. Thus, when D=1, Q=0, Q+=1 J, K = 1, x D=0, Q+=0 J, K = 0, x D=1, Q+=1 J, K = x, 0 D=0, Q=1, Q+=0 J, K = x, 1. J D CLK K x x 1 0 D-FF Q

D J-K Example 2: should work like a J-K Excitation Table for D Q Q+ 0 0 0 1 1 JK Q 0 1 D 0 1 00 01 11 10 0 0 1 1 0 0 1 J 0 0 1 1 K 0 0 1 1 Q 0 1 0 1 Q+ 0 1 0 0 1 1 1 0 K TT for J-K 1 J-K FF/Latch Q J CLK Logic CLK Function is K D J D Q Q

(C) Counter Design • A counter is a special case of an FSM that cycles through its states on receiving triggering clock pluses. • It does not have any external data I/Ps. Reset 100 E A B 000 No external I/Ps D 011 Counter O/P Logic Next State bits 001 C 010 FFs n n CLK • The states need to be encoded by binary bits.

State Transition Diagram and Table for a 3 -bit Binary Up-Counter Reset Synthesis (3 -Bit Up Counter) 000 Input Present State 111 001 110 010 101 011 100 C 0 0 1 1 (a) State Transition Diagram FF Excitation Table Revisited Q 0 0 1 1 Q+ 0 1 R x 0 1 0 S 0 1 0 x J 0 1 x x K x x 1 0 T 0 1 1 0 D 0 1 B 0 0 1 1 A 0 1 0 1 Output Next State C+ 0 0 0 1 1 0 B + A+ 0 1 1 0 0 Toggle Flip-Flop Inputs TC TB TA 0 0 1 0 1 1 0 0 1 1 1 1 (b) State Transition Table (What next state will be given the current state. ) Excitation table for R-S, J-K, T, and D Flip-Flops

From excitation table for FF inputs, get K-map for the FF inputs. CB A 0 1 00 01 11 10 1 1 1 1 TA=1 CB 00 01 11 10 A 0 0 0 1 1 0 1 TC=AB CB A 0 1 00 01 11 10 0 1 0 1 K-maps for Up-Counter Using Toggle Flip-Flops. TB=A Obtain logic expr. for FF I/Ps (as functions of current state bits A, B, C, --- A=QA, B=QB, C=QC) and realize the counter

Counters with More Complex Sequencing (Non-Consecutive Binary Outputs) Present State 000 110 010 101 011 State Transition Diagram Implementation Using J-K FFs: Present State C B A 0 0 0 1 1 1 0 0 1 1 1 Next State + C B+ 0 1 x x 0 1 1 0 x x 1 1 0 0 x x A+ 0 x 1 1 x 0 0 x JC 0 x 0 1 x x C 0 0 1 1 Remapped Next State KC JB KB x 1 x x x 0 x x 1 x x x 0 1 x 1 x x x B 0 0 1 1 A 0 1 0 1 Next State C+ 0 x 0 1 x 1 0 x B + A+ 1 0 x x 1 1 0 1 x x 1 0 0 0 x x State Transition Table JA KA 0 x x x 1 x x 0 x x x 1 0 x x x State Transition Table and Remapped Next-State Functions Q 0 0 1 1 Q+ 0 1 J K 0 x 1 x 0 J-K Flip-Flop Excitation Table

Next State Functions CB 00 A 0 0 1 x A CB 0 1 01 11 10 0 1 x x 00 01 11 10 1 x x x 1 CB 00 A 0 0 1 x 01 1 x 11 0 x CB A 00 x x JC A JB 10 x x JA x x 0 1 CB 0 1 01 x x 11 1 x 10 x 0 KC 00 01 11 10 x x 0 1 1 x x x CB 00 A 0 x 1 x 0 Remapped K-Maps for J-K Implementation. 11 x x KB 10 x 1 KA

Actual Implementation ( Using J-K) + A J Q CLK K Q C KB J Q CLK K Q B JA J Q CLK K Q C Count signal A C B KB JA J-K Flip-Flop Implementation of 3 Bit Counter. A