ECE 465 Introduction to CPLDs and FPGAs Shantanu

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ECE 465 Introduction to CPLDs and FPGAs Shantanu Dutt ECE Dept. University of Illinois

ECE 465 Introduction to CPLDs and FPGAs Shantanu Dutt ECE Dept. University of Illinois at Chicago Acknowledgement: Extracted from lecture notes of Dr. Mohamed M. Elkhatib, German University of Cairo and Prof. Russell Tessier, Univ. of Massachusetts. Some modfications and additions done by Prof. Dutt.

CPLD Families

CPLD Families

CPLD Block Diagram 1 FF 0 FF FF FF 0 1 An individual switch

CPLD Block Diagram 1 FF 0 FF FF FF 0 1 An individual switch In a crossbar is a diamond switch O/Ps Programmable switch for interconnecting various FBs I/Ps Crossbar Switch Function block (~ PLA w/ 1 o/p that can be FF’ed)

CPLD Function Block Extra function (e. g. , g, h) i/ps for OR term

CPLD Function Block Extra function (e. g. , g, h) i/ps for OR term 2: 1 Mux Example function f= ab+bc’+g+h D-FF Literal inputs (e. g. , a, b, c) PLA-like AND array

Field Programmable Gate Arrays (FPGAs)

Field Programmable Gate Arrays (FPGAs)

FPGA Types (Anti-fuse technology)

FPGA Types (Anti-fuse technology)

FPGA Families

FPGA Families

SRAM-type FPGA Interconnect Architecture Diamond switch Horizontal routing (interconnect) channel PSM: Programmable Switch Matrix

SRAM-type FPGA Interconnect Architecture Diamond switch Horizontal routing (interconnect) channel PSM: Programmable Switch Matrix (for making connections between interconnects of different channels). The structure shown only allows i-to-i connections Vertical routing channels CLB: Configuration Logic Block (programmable logic cell)

SRAM-type FPGA Interconnect Architecture (contd) Cell Connection Matrix (CCM) PSM

SRAM-type FPGA Interconnect Architecture (contd) Cell Connection Matrix (CCM) PSM

Configuration Logic Block (CLB) • 5 -i/p function implemented using G, F and H

Configuration Logic Block (CLB) • 5 -i/p function implemented using G, F and H LUTs (Look Up Tables) using Shannon’s Expansion: p(a, b, c, d, e) = a p(1, b, c, d, e) + a’ p(0, b, c, d, e) = a q(b, c, d, e) + a’r(b, c, d, e). q( ) impl. using LUT G, r impl. using LUT F and p=ag + a’h impl. using LUT H • The LUT o/ps can go through a FF (for seq. ckt design) or bypass it for a combinational o/p • This is called technology mapping: mapping the logic to CLB logic components

Technology Mapping

Technology Mapping

Programming a CLB (contd)

Programming a CLB (contd)

Components of Modern FPGAs

Components of Modern FPGAs

Digital System: Implementation Spectrum Microprocessor Software Reconfigurable Hardware Firmware ASIC Hardware – ASIC gives

Digital System: Implementation Spectrum Microprocessor Software Reconfigurable Hardware Firmware ASIC Hardware – ASIC gives high performance at cost of inflexibility. – Processor is very flexible but not tuned to the application. – Reconfigurable hardware is a nice compromise.

Simplified FPGA Logic Element

Simplified FPGA Logic Element

High-level Compilers & FPGAs –Difficult to estimate hardware resources. –Some parts of program more

High-level Compilers & FPGAs –Difficult to estimate hardware resources. –Some parts of program more appropriate for processor (hardware/software codesign). –Compiler must parallelize computation across many resources. –Engineers like to write in C/VHDL/Verilog rather than pushing little blocks around. for (i = 0; i<n, i++) { c[i] = a[i] + b[i] } Some success stories

Translating a Design to an FPGA RTL. . C = A+B. Array Circuit A

Translating a Design to an FPGA RTL. . C = A+B. Array Circuit A B + C – CAD to translate circuit from text description to physical implementation well understood. – Most current FPGA designers use register-transfer level specification (allocation and scheduling) – Same basic steps as ASIC design.

Circuit Compilation & Implementation: Basic Steps 1. Technology Mapping LUT 2. Placement LUT ?

Circuit Compilation & Implementation: Basic Steps 1. Technology Mapping LUT 2. Placement LUT ? Assign a logical LUT to a physical location. 3. Routing 4. Convert all implementation “details” to FPGA programming info (configuration bits): LUT RAM bits, CCM & PSM FF/SRAM bits, etc. • Can store config bits on disk or ROM and load into FPGA as needed • Can thus use the FPGA to implement multiple digital systems (at different times or sometimes simultaneously in different FPGA partitions) Select wire segments and switches for Interconnection.

Technology Mapping: A Simple Example Made of Full Adders A B Co FA A+B

Technology Mapping: A Simple Example Made of Full Adders A B Co FA A+B = D Ci S Logic synthesis tool reduces circuit to SOP form S = ABCi + ABCi A B Ci LUT Co A B Ci Co = ABCi + ABCi LUT S

Processor + FPGA Three possibilities Proc chip daughtercard FPGA Backplane bus (e. g. PCI)

Processor + FPGA Three possibilities Proc chip daughtercard FPGA Backplane bus (e. g. PCI) 1. FPGA serves as coprocessor for data intensive applications – possible project. Proc FPGA chip 2. FPGA serves as embedded digital system for lower latency processing. “Reconfigurable Functional Unit”