EE 4800 CMOS Digital IC Design Analysis Lecture

  • Slides: 25
Download presentation
EE 4800 CMOS Digital IC Design & Analysis Lecture 11 Sequential Circuit Design Zhuo

EE 4800 CMOS Digital IC Design & Analysis Lecture 11 Sequential Circuit Design Zhuo Feng 11. 1 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Outline ■ ■ Sequencing Element Design Max and Min-Delay Clock Skew 11. 2 Z.

Outline ■ ■ Sequencing Element Design Max and Min-Delay Clock Skew 11. 2 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Sequencing ■ Combinational logic ► output depends on current inputs ■ Sequential logic ►

Sequencing ■ Combinational logic ► output depends on current inputs ■ Sequential logic ► output depends on current and previous inputs ► Requires separating previous, current, future ► Called state or tokens ► Ex: FSM, pipeline 11. 3 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Sequencing Cont. ■ If tokens moved through pipeline at constant speed, no sequencing elements

Sequencing Cont. ■ If tokens moved through pipeline at constant speed, no sequencing elements would be necessary ■ Ex: fiber-optic cable ► Light pulses (tokens) are sent down cable ► Next pulse sent before first reaches end of cable ► No need for hardware to separate pulses ► But dispersion sets min time between pulses ■ This is called wave pipelining in circuits ■ In most circuits, dispersion is high ► Delay fast tokens so they don’t catch slow ones. 11. 4 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Sequencing Overhead ■ Use flip-flops to delay fast tokens so they move through exactly

Sequencing Overhead ■ Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. ■ Inevitably adds some delay to the slow tokens ■ Makes circuit slower than just the logic delay ► Called sequencing overhead ■ Some people call this clocking overhead ► But it applies to asynchronous circuits too ► Inevitable side effect of maintaining sequence 11. 5 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Sequencing Elements ■ Latch: Level sensitive ► a. k. a. transparent latch, D latch

Sequencing Elements ■ Latch: Level sensitive ► a. k. a. transparent latch, D latch ■ Flip-flop: edge triggered ► A. k. a. master-slave flip-flop, D register ■ Timing Diagrams ► Transparent ► Opaque ► Edge-trigger 11. 6 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Sequencing Elements ■ Latch: Level sensitive ► a. k. a. transparent latch, D latch

Sequencing Elements ■ Latch: Level sensitive ► a. k. a. transparent latch, D latch ■ Flip-flop: edge triggered ► A. k. a. master-slave flip-flop, D register ■ Timing Diagrams ► Transparent ► Opaque ► Edge-trigger 11. 7 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Latch Design ■ Pass Transistor Latch ■ Pros + Tiny + Low clock load

Latch Design ■ Pass Transistor Latch ■ Pros + Tiny + Low clock load ■ Cons ► Vt drop ► nonrestoring ► backdriving Used in 1970’s ► output noise sensitivity ► dynamic ► diffusion input 11. 8 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Latch Design ■ Transmission gate + No Vt drop - Requires inverted clock 11.

Latch Design ■ Transmission gate + No Vt drop - Requires inverted clock 11. 9 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Latch Design ■ Inverting buffer + Restoring + No backdriving + Fixes either ▼

Latch Design ■ Inverting buffer + Restoring + No backdriving + Fixes either ▼ Output noise sensitivity ▼ Or diffusion input ► Inverted output 11. 10 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Latch Design ■ Tristate feedback + Static ► Backdriving risk ■ Static latches are

Latch Design ■ Tristate feedback + Static ► Backdriving risk ■ Static latches are now essential 11. 11 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Latch Design ■ Buffered input + Fixes diffusion input + Noninverting 11. 12 Z.

Latch Design ■ Buffered input + Fixes diffusion input + Noninverting 11. 12 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Latch Design ■ Buffered output + No backdriving ■ Widely used in standard cells

Latch Design ■ Buffered output + No backdriving ■ Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1. 5 – 2 FO 4 delays) - High clock loading 11. 13 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Latch Design ■ Datapath latch + Smaller, faster - unbuffered input 11. 14 Z.

Latch Design ■ Datapath latch + Smaller, faster - unbuffered input 11. 14 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Flip-Flop Design ■ Flip-flop is built as pair of back-to-back latches 11. 15 Z.

Flip-Flop Design ■ Flip-flop is built as pair of back-to-back latches 11. 15 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Enable ■ Enable: ignore clock when en = 0 ► Mux: increase latch D-Q

Enable ■ Enable: ignore clock when en = 0 ► Mux: increase latch D-Q delay ► Clock Gating: increase en setup time, skew 11. 16 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Reset ■ Force output low when reset asserted ■ Synchronous vs. asynchronous 11. 17

Reset ■ Force output low when reset asserted ■ Synchronous vs. asynchronous 11. 17 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Set / Reset ■ Set forces output high when enabled ■ Flip-flop with asynchronous

Set / Reset ■ Set forces output high when enabled ■ Flip-flop with asynchronous set and reset 11. 18 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Sequencing Methods ■ Flip-flops ■ 2 -Phase Latches ■ Pulsed Latches 11. 19 Z.

Sequencing Methods ■ Flip-flops ■ 2 -Phase Latches ■ Pulsed Latches 11. 19 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Timing Diagrams Contamination and Propagation Delays tpd Logic Prop. Delay tcd Logic Cont. Delay

Timing Diagrams Contamination and Propagation Delays tpd Logic Prop. Delay tcd Logic Cont. Delay tpcq Latch/Flop Clk-Q Prop Delay tccq Latch/Flop Clk-Q Cont. Delay tpdq Latch D-Q Prop Delay tpcq Latch D-Q Cont. Delay tsetup Latch/Flop Setup Time thold Latch/Flop Hold Time 11. 20 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Max-Delay: Flip-Flops 11. 21 Z. Feng MTU EE 4800 CMOS Digital IC Design &

Max-Delay: Flip-Flops 11. 21 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Max Delay: Pulsed Latches 11. 22 Z. Feng MTU EE 4800 CMOS Digital IC

Max Delay: Pulsed Latches 11. 22 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Min-Delay: Flip-Flops 11. 23 Z. Feng MTU EE 4800 CMOS Digital IC Design &

Min-Delay: Flip-Flops 11. 23 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Clock Skew ■ We have assumed zero clock skew ■ Two types of clock

Clock Skew ■ We have assumed zero clock skew ■ Two types of clock skews: ► Negative skew: sending register receives the clock earlier than the receiving register ► Positive skew: receiving register gets the clock earlier than the sending register. ■ Clocks really have uncertainty in arrival time ► Decreases maximum propagation delay ► Increases minimum contamination delay ► Decreases time borrowing 11. 24 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

Skew: Flip-Flops 11. 25 Z. Feng MTU EE 4800 CMOS Digital IC Design &

Skew: Flip-Flops 11. 25 Z. Feng MTU EE 4800 CMOS Digital IC Design & Analysis 2010

EE 4800 CMOS Digital IC Design Analysis LectureEE 4800 CMOS Digital IC Design Analysis Lecture
EE 4800 CMOS Digital IC Design Analysis LectureEE 4800 CMOS Digital IC Design Analysis Lecture
EE 4800 CMOS Digital IC Design Analysis LectureEE 4800 CMOS Digital IC Design Analysis Lecture
EE 4800 CMOS Digital IC Design Analysis LectureEE 4800 CMOS Digital IC Design Analysis Lecture
EE 4800 CMOS Digital IC Design Analysis LectureEE 4800 CMOS Digital IC Design Analysis Lecture
EE 4800 CMOS Digital IC Design Analysis LectureEE 4800 CMOS Digital IC Design Analysis Lecture
EE 4800 CMOS Digital IC Design Analysis LectureEE 4800 CMOS Digital IC Design Analysis Lecture
CMOS VLSI Design Digital Design CMOS VLSI 1CMOS VLSI Design Digital Design CMOS VLSI 1
Outline Introduction CMOS devices CMOS technology CMOS logicOutline Introduction CMOS devices CMOS technology CMOS logic
Digital CMOS Logic Circuits CMOS digital circuits smallDigital CMOS Logic Circuits CMOS digital circuits small
CMOS VLSI Digital Design CMOS VLSI 1 OverviewCMOS VLSI Digital Design CMOS VLSI 1 Overview
Introduction to CMOS VLSI Design Lecture 3 CMOSIntroduction to CMOS VLSI Design Lecture 3 CMOS
Introduction to CMOS VLSI Design Lecture 3 CMOSIntroduction to CMOS VLSI Design Lecture 3 CMOS
Introduction to CMOS VLSI Design Lecture 5 CMOSIntroduction to CMOS VLSI Design Lecture 5 CMOS
Introduction to CMOS VLSI Design Lecture 5 CMOSIntroduction to CMOS VLSI Design Lecture 5 CMOS
Bab 13 Rangkaian Logika Digital CMOS Inverter CMOSBab 13 Rangkaian Logika Digital CMOS Inverter CMOS
CMOS Digital Integrated Circuits Lec 11 Sequential CMOSCMOS Digital Integrated Circuits Lec 11 Sequential CMOS
CMOS Digital Integrated Circuits Lec 14 LowPower CMOSCMOS Digital Integrated Circuits Lec 14 LowPower CMOS
CMOS Digital Integrated Circuits Lec 7 CMOS InvertersCMOS Digital Integrated Circuits Lec 7 CMOS Inverters
CMOS Digital Integrated Circuits Lec 10 Combinational CMOSCMOS Digital Integrated Circuits Lec 10 Combinational CMOS
CMOS Digital Integrated Circuits Lec 6 CMOS InvertersCMOS Digital Integrated Circuits Lec 6 CMOS Inverters
Introduction to CMOS VLSI Design CMOS Transistor TheoryIntroduction to CMOS VLSI Design CMOS Transistor Theory
EE 4271 VLSI Design CMOS Combinational Gate CMOSEE 4271 VLSI Design CMOS Combinational Gate CMOS
CMOS VLSI Analog Design CMOS VLSI 1 OutlineCMOS VLSI Analog Design CMOS VLSI 1 Outline