CMOS Digital Integrated Circuits Lec 7 CMOS Inverters

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CMOS Digital Integrated Circuits Lec 7 CMOS Inverters: Dynamic Analysis and Design 1 CMOS

CMOS Digital Integrated Circuits Lec 7 CMOS Inverters: Dynamic Analysis and Design 1 CMOS Digital Integrated Circuits

CMOS Inverters – Dynamic Analysis and Design n Goals • Understand the detail dynamic

CMOS Inverters – Dynamic Analysis and Design n Goals • Understand the detail dynamic analysis of the CMOS inverter. • Understand one set of design form CMOS equations. • Understand the basic CMOS design process using the CMOS static and CMOS design form dynamic equations. 2 CMOS Digital Integrated Circuits

CMOS Dynamic Analysis Capacitance Model for CMOS VDD Cgs, p Csb, p Cdb, p

CMOS Dynamic Analysis Capacitance Model for CMOS VDD Cgs, p Csb, p Cdb, p Vin Vout Cgd, p Cgd, n FO Cdb, n Cgs, n 3 Csb, n Cint Cg CMOS Digital Integrated Circuits

CMOS Dynamic Analysis Capacitance Model for CMOS • The aggregate capacitance driven by the

CMOS Dynamic Analysis Capacitance Model for CMOS • The aggregate capacitance driven by the output node of a CMOS inverter is in detail working from left to right, • Cload = Cinput + Cint + Cg in which Cinput = Cgd, n + Cgd, p + Cdb, n + Cdb, p (intrinsic component) Cint = interconnect capacitance (extrinsic component) Cg = thin-oxide capacitance over the gate area 4 CMOS Digital Integrated Circuits

CMOS Dynamic Analysis Delay-Time Definitions Vin idealized step input VOH V 50% = VOL+(VOH-VOL)/2.

CMOS Dynamic Analysis Delay-Time Definitions Vin idealized step input VOH V 50% = VOL+(VOH-VOL)/2. = (VOH+VOL)/2 V 50% VOL Vout t τPHL = t 1 -t 0 VOH τPLH = t 3 -t 2 V 50% τP = (τPHL+τPLH)/2 VOL Vout t 0 t 1 t t 2 t 3 V 10% = VOL+0. 1(VOH-VOL) V 90% = VOL+0. 9(VOH-VOL) τfall = t. B-t. A V 10% t. A 5 t. B t. C t. D t τrise = t. C-t. D CMOS Digital Integrated Circuits

CMOS Dynamic Analysis Delay-Time Calculation (First Order Estimates) • The simplest approach of calculating

CMOS Dynamic Analysis Delay-Time Calculation (First Order Estimates) • The simplest approach of calculating the propagation delay is based on estimating the average capacitance current during charge down/up. where 6 CMOS Digital Integrated Circuits

CMOS Dynamic Analysis Delay-Time Calculation (More Accurate)(1/4) • The propagation delay can be found

CMOS Dynamic Analysis Delay-Time Calculation (More Accurate)(1/4) • The propagation delay can be found more accurately by solving the state equation of the output node. The current flowing through Cload is a function Vout as i. D, p Vin i. C Vout i. D, n • τPHL: PMOS is off. The equivalent circuit during high-to-low output transition is i. D, n Vin 7 n. MOS Vout Cload CMOS Digital Integrated Circuits

CMOS Dynamic Analysis Delay-Time Calculation (2/4) The n. MOS operates in two regions, saturation

CMOS Dynamic Analysis Delay-Time Calculation (2/4) The n. MOS operates in two regions, saturation and linear, during the interval of τPHL. Vout VOH=VDD VOH -VT, n V 50% n. MOS in saturation n. MOS in linear region t 0 t 1’ t 1 t • Saturation Region i. D, n=(kn/2)(Vin-VT, n)2=(kn/2)(VOH-VT, n)2 » Plug i. D, n into Cload d. Vout/dt=-i. D, n, and integrate both sides, we get t 1’-t 0 = 2 Cload. VT, n/[kn(VOH-VT, n)2] 8 CMOS Digital Integrated Circuits

CMOS Dynamic Analysis Delay-Time Calculation (3/4) • Linear Region i. D, n= (kn/2)[2(Vin-VT, n)Vout-Vout

CMOS Dynamic Analysis Delay-Time Calculation (3/4) • Linear Region i. D, n= (kn/2)[2(Vin-VT, n)Vout-Vout 2] = (kn/2)[2(VOH-VT, n)Vout-Vout 2] » Plug i. D, n into Cload d. Vout/dt=-i. D, n, and integrate both sides, we have • Finally, since VOH=VDD and VOL=0, we have Vout VOH -VT, n V 50% 9 n. MOS in saturation n. MOS in linear region t 0 t 1’ t 1 t CMOS Digital Integrated Circuits

CMOS Dynamic Analysis Delay-Time Calculation (4/4) • τPLH: NMOS is off. The equivalent circuit

CMOS Dynamic Analysis Delay-Time Calculation (4/4) • τPLH: NMOS is off. The equivalent circuit during low-to-high output VDD transition is Vin p. MOS i. D, p Vout Cload With the similar way (t 0→t 1’→t 1∕ 0→|VT, p|→V 50%∕linear →saturation), we can have 10 CMOS Digital Integrated Circuits

CMOS Inverter Design n Design for Performance • Keep capacitance small • Increase transistor

CMOS Inverter Design n Design for Performance • Keep capacitance small • Increase transistor size » Watch out for self-loading! • Increase VDD (? ? ) 11 CMOS Digital Integrated Circuits

CMOS Inverter Design Delay as a Function of VDD • VDD increases → τPHL/τPLH

CMOS Inverter Design Delay as a Function of VDD • VDD increases → τPHL/τPLH decreases. However, the power consumption also increases. 5. 5 5 τp. HL(normalized) 4. 5 4 3. 5 3 2. 5 2 1. 5 1 0. 8 1 1. 2 1. 4 1. 6 1. 8 2 2. 4 VDD(V) 12 CMOS Digital Integrated Circuits

CMOS Inverter Design Device Sizing (1/5) 3. 8 x 10 -11 (for fixed load)

CMOS Inverter Design Device Sizing (1/5) 3. 8 x 10 -11 (for fixed load) 3. 6 3. 4 τp(sec) 3. 2 3. 0 Self-loading effect: Intrinsic capacitances dominate 2. 8 2. 6 2. 4 2. 2 2. 0 13 2 4 6 8 S 10 12 14 CMOS Digital Integrated Circuits

CMOS Inverter Design Device Sizing (2/5) n NMOS/PMOS Ratio -11 5 x 10 PLH

CMOS Inverter Design Device Sizing (2/5) n NMOS/PMOS Ratio -11 5 x 10 PLH PHL R = Wp / W n 4 p (sec) 4. 5 P 3. 5 3 14 1 1. 5 2 2. 5 3 R 3. 5 4 4. 5 5 CMOS Digital Integrated Circuits

CMOS Inverter Design Device Sizing (3/5) Self-Loading Effect Cload = Cgd, n(Wn) + Cgd,

CMOS Inverter Design Device Sizing (3/5) Self-Loading Effect Cload = Cgd, n(Wn) + Cgd, p(Wp) + Cdb, n(Wn) + Cdb, p(Wp) + Cint +Cg = f(Wn, Wp) • Using the junction capacitance expressions in Chapter 3, we have Cdb, n = (Wn. Ddrain+xj. Ddrain)Cj 0, n. Keq, n+(Wn+2 Ddrain)Cjsw, n. Keq, n Cdp, n = (Wp. Ddrain+xj. Ddrain)Cj 0, p. Keq, p+(Wp+2 Ddrain)Cjsw, p. Keq, p • Therefore, Cload can be rewritten as Cload = α 0+ αn. Wn+ αp. Wp where 0 = Ddrain(2 Cjsw, n. Keq, n+2 Cjsw, p. Keq, p+xj. Cj 0, n. Keq, n+xj. Cj 0, p. Keq, p)+Cint+Cg n = Keq, n(Cj 0, n. Ddrain+Cjsw, n) p = Keq, p(Cj 0, p. Ddrain+Cjsw, p) 15 CMOS Digital Integrated Circuits

CMOS Inverter Design Device Sizing (4/5) • Therefore, τPHL and τPLH are • The

CMOS Inverter Design Device Sizing (4/5) • Therefore, τPHL and τPLH are • The ratio between the channel widths Wn and Wp is usually dictated by other design constraints such as noise margins and the logic inversion threshold. Let’s this transistor aspect ratio be defined as R ≡ Wp/Wn. Then, the propagation delay can be represented as 16 CMOS Digital Integrated Circuits

CMOS Inverter Design Device Sizing (5/5) • As we continue increase the values of

CMOS Inverter Design Device Sizing (5/5) • As we continue increase the values of Wn and Wp, the propagation delay will asymptotically approach a limit value for lager Wn and Wp, • The propagation delay times cannot be reduced beyond the above limits, and the limit is independent of the extrinsic capacitances. 17 CMOS Digital Integrated Circuits

CMOS Inverter Design Impact of Rise Time on Delay 0. 35 τp. H L

CMOS Inverter Design Impact of Rise Time on Delay 0. 35 τp. H L (nsec) 0. 3 0. 25 0. 2 0. 15 0 0. 2 0. 4 0. 6 τ rise (nsec) 0. 8 1 Propagation delay increases since both PMOS and NMOS are on during the charge-up and chargedown events. 18 CMOS Digital Integrated Circuits

CMOS Inverter Design Impact of Channel Velocity Saturation n n 19 The drain current

CMOS Inverter Design Impact of Channel Velocity Saturation n n 19 The drain current is linearly dependent on VGS Isat = κWn (VGS-VT) Propagation delay only has a weak dependence on the supply voltage VDD CMOS Digital Integrated Circuits

CMOS Dynamic Analysis Dynamic Power Dissipation (1/2) • The dynamic power dissipation can be

CMOS Dynamic Analysis Dynamic Power Dissipation (1/2) • The dynamic power dissipation can be derived as follows. Pdyn, avg = VDD IDD, avg • With IDD, avg taken over one clock period T. The capacitance current which equals the current from the power supply (assuming IDn = 0 during charging) is • Rearranging and integrating over one clock period T • Gives IDD, avg T = Cload VDD 20 CMOS Digital Integrated Circuits

CMOS Dynamic Analysis Dynamic Power Dissipation (2/2) • Solving for IDD, avg and substituting

CMOS Dynamic Analysis Dynamic Power Dissipation (2/2) • Solving for IDD, avg and substituting in Pavg: • It should be noted here the our simple Cload may underestimate the power dissipated. • In terms of SPICE simulation, the authors’ offer a circuit called power meter. 21 CMOS Digital Integrated Circuits