Dynamic and Pass Transistor Logic Prof Vojin G

Dynamic and Pass -Transistor Logic Prof. Vojin G. Oklobdzija References (used for creation of the presentation material): 1. 2. 3. Masaki, “Deep-Submicron CMOS Warms Up to High-Speed Logic”, IEEE Circuits and Devices Magazine, November 1992. Krambeck, C. M. Lee, H. S. Law, “High-Speed Compact Circuits with CMOS”, IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982. V. G. Oklobdzija, R. K. Montoye, “Design-Performance Trade-Offs in CMOSDomino Logic”, IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April 1986. Fall 2004 Prof. V. G. Oklobdzija: High. Performance System Design

References: 4. 5. 6. 7. Fall 2004 Goncalves, H. J. De. Man, “NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures”, IEEE Journal of Solid. State Circuits, Vol. SC-18, No 3, June 1983. L. G. Heller, et al, “Cascode Voltage Switch Logic: A Differential CMOS Logic Family”, in 1984 Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 1984. L. C. M. G. Pfennings, et al, “Differential Split-Level CMOS Logic for Subnanosecond Speeds”, IEEE Journal of Solid-State Circuits, Vol. SC-20, No 5, October 1985. K. M. Chu, D. L. Pulfrey, "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No. 4, August 1987. Prof. V. G. Oklobdzija: High-Performance System Design 2

References: Pass-Transistor Logic: 8. 9. 10. 11. 12. Fall 2004 S. Whitaker, “Pass-transistor networks optimize n-MOS logic”, Electronics, September 1983. K. Yano, et al, “A 3. 8 -ns CMOS 16 x 16 -b Multiplier Using Complementary Pass-Transistor Logic”, IEEE Journal of Solid. State Circuits, Vol. 25, No 2, April 1990. K. Yano, et al, “Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1 -4, 1994. M. Suzuki, et al, “A 1. 5 ns 32 b CMOS ALU in Double Pass. Transistor Logic”, Journal of Solid-State Circuits, Vol. 28. No 11, November 1993. N. Ohkubo, et al, “A 4. 4 -ns CMOS 54 x 54 -b Multiplier Using Pass-transistor Multiplexer”, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1 -4, 1994. Prof. V. G. Oklobdzija: High-Performance System Design 3

References: 13. V. G. Oklobdzija and B. Duchêne, “Pass-Transistor Dual Value Logic For Low-Power CMOS, ” Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31 -June 2 nd, 1995. 14. F. S. Lai, W. Hwang, “Differential Cascode Voltage Switch with the Pass-Gate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems”, Proceedings of the 1993 International Symposium on VLSI Technology, Taipei, Taiwan, June 2 -4, 1995 15. A. Parameswar, H. Hara, T. Sakurai, “A Swing Restored Pass. Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications”, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1 -4, 1994. 16. T. Fuse, et al, “ 0. 5 V SOI CMOS Pass-Gate Logic”, Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco February 8, 1996. Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 4

Pass-Transistor Logic Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 5

Pass-Transistor Logic (a) (b) (a) XOR function implemented with pass-transistor circuit (b) Karnaough map showing derivation of the XOR function Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 6

Pass-Transistor Logic General topology of passtransistor function generator Karnaough map of 16 possible functions that can be realized Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 7

Pass-Transistor Logic Function generator implemented with passtransistor logic Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 8

Pass-Transistor Logic Threshold voltage drop at the output of the passtransistor gate Fall 2004 Voltage drop does not exceed Vth when there are multiple transistors in the path Prof. V. G. Oklobdzija: High-Performance System Design 9

Pass-Transistor Logic Elimination of the threshold voltage drop by: (a) pairing n. MOS transistor with a p. MOS (b) using a swing-restoring inverter Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 10

Complementary Pass-Transistor Logic (CPL) Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 11

Basic logic functions in CPL Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 12

CPL Logic XOR gate Sum circuit CPL provides an efficient implementation of XOR function Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 13

CPL Inverter Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 14

Double Pass-Transistor Logic (DPL): AND/NAND XOR/XNOR Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 15

Double Pass-Transistor Logic (DPL): XOR One bit full-adder: Sum circuit Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 16

Double Pass-Transistor Logic (DPL): DPL Full Adder The critical path traverses two transistors only (not counting the buffer) Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 17

Formal Method for CPL Logic Derivation Markovic et al. 2000 (a) Cover the Karnaugh-map with largest possible cubes (overlapping allowed) (b) Express the value of the function in each cube in terms of input signals (c) Assign one branch of transistor(s) to each of the cubes and connect all the branches to one common node, which is the output of NMOS pass-transistor network Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 18

Formal Method for P-T Logic Derivation Complementary function can be implemented from the same circuit structure by applying complementarity principle: Complementarity Principle: Using the same circuit topology, with pass signals inverted, complementary logic function is constructed in CPL. By applying duality principle, a dual function is synthesized: Duality Principle: Using the same circuit topology, with gate signals inverted, dual logic function is constructed. Following pairs of basic functions are dual: AND-OR (and vice-versa) NAND-NOR (and vice-versa) XOR and XNOR are self-dual (dual to itself) Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 19

Derivation of P-T Logic Copmplementarity: AND NAND; Fall 2004 Duality: AND OR Prof. V. G. Oklobdzija: High-Performance System Design 20

Derivation of CPL Logic Complementarity: AND NAND Duality: AND OR NAND NOR Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 21

Two-Input Function with balanced input load Each input A, B, or A, B has FO=2 Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 22

Derivation of CPL Logic (a) XOR function Karnaugh map, (b) XOR/XNOR circuit Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 23

Synthesis of three-input CPL logic (a) AND function Karnaugh map, (b) AND/NAND circuit Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 24

Circuit realization of 3 -input AND/NAND function Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 25

Double Pass-Transistor Logic (DPL): Synthesis Rules 1. Two NMOS branches can not be overlapped covering logic 1 s. Similarly, two PMOS branches can not be overlapped covering logic 0 s. 2. Pass signals are expressed in terms of input signals or supply. Every input vector has to be covered with exactly two branches. At any time, excluding transitions, exactly two transistor branches are active (any of the pairs NMOS/PMOS, NMOS/NMOS and PMOS/PMOS are possible), i. e. they both provide output current. Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 26

Double Pass-Transistor Logic (DPL): Synthesis Rules Complementarity Principle: Complementary logic function in DPL is generated after the following modifications: • Exchange PMOS and NMOS devices. Invert all pass and gate signals Duality Principle: Dual logic function in DPL is generated when: • PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged. Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 27

DPL Synthesis: (a) AND function Karnaugh map Fall 2004 (b) AND/NAND circuit Prof. V. G. Oklobdzija: High-Performance System Design 28

DPL Synthesis: OR/NOR circuit Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 29

XOR/XNOR in DPL Circuit realization of 2 -input XOR/XNOR function in DPL, with balanced input load Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 30

DPL Synthesis: AND function Karnaugh map Complementarit y Principle: Exchange PMOS and NMOS devices. Invert all pass and gate signals AND NAND AND/NAND circuit Duality Principle: PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged: AND OR NAND NOR Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 31

DVL Logic Advantage of CPL and DPL were recognized in DVL which attempts to generalize pass-transistor networks and minimize the number of transistors and input loads. Rules: 1. Cover all input vectors that produce “ 0” at the output, with largest possible cubes (overlapping allowed) and represent those cubes with NMOS devices, with sources connected to GND 2. Repeat step 1 for input vectors that produce “ 1” at the output and represent those cubes with PMOS devices, with sources connected to Vdd 3. Finish with mapping input vectors, not mapped in steps 1 and 2 (overlapping with cubes from steps 1 and 2 allowed) that produce” 0” or “ 1” at the output. Represent those cubes with parallel NMOS (good pull-down) and PMOS (good pull-up) branches, with sources connected to one of the input signals Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 32

Two input AND/NAND in DVL Logic Circuit realization of 2 -input AND/NAND function in DVL Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 33

Two input OR/NOR in DVL Logic Circuit realization of 2 -input OR/NOR circuit in DVL XOR/XNOR realization is identical to that of DPL. Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 34

Three input AND function in DVL Logic Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 35

Three input OR/NOR in DVL Circuit realization of 3 -input OR/NOR functions in DVL Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 36

Comparison TABLE I. Realizations of 3 -input function F=B’C+ABC’ # of Signal Realization input termination signals CMOS 9 10 G Trans. Count Output load 10 4 S DVL (b) 9 8 G + 6 S 8 6 S DVL (c) 9 7 G + 3 S 7 4 S Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 37

Comparison Realizations of 3 -input function F=B’C+ABC’ (a) Standard CMOS, (b) DVL, (c) DVL Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 38

Conclusion General rules for synthesizing logic gates in three representative pass-transistor techniques were shown. An algorithmic way for generation of various circuit topologies (complementary and dual circuits) is discussed. Generation of circuits with balanced input loads is suitable for library based designs is possible if complementarity and commutative principles are applied. This lays the foundation for development of computer aided design (CAD) tools capable of generating fast and power-efficient pass-transistor logic. Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 39