COMP 541 Combinational Logic I Montek Singh Jan
COMP 541 Combinational Logic - I Montek Singh Jan 17 24, 2018
Today ã Basics of digital logic (review) l Basic gates l Combinational logic l Various representations Ø Boolean algebra Ø Truth tables Ø Karnaugh Maps (“K-Maps”) Ø Circuit schematic diagrams Ø Hardware Description Languages (HDL) 2
Binary Logic ã Binary variables l Can be 0 or 1 (True or False, low or high) l Variables named with single letters in examples Ø Really use words when designing circuits 3
Logic Gates ã Perform logic functions: l inversion (NOT), AND, OR, NAND, NOR, etc. ã Single-input: l NOT gate l buffer (non-inverting) ã Two-input: l AND, OR, XOR, NAND, NOR, XNOR ã Multiple-input l Most 2 -input gates also have multi-input flavors 4
Single-Input Logic Gates 5
Two-Input Logic Gates 6
More Two-Input Logic Gates 7
More Two-Input Logic Gates 8
Multiple-Input Logic Gates 9
Multiple-Input Logic Gates 10
NAND is Universal ã Can express any Boolean Function 11
Using NAND as Invert-OR ã De. Morgan’s Law: ã Also reverse inverter diagram for clarity 12
NOR Also Universal ã Dual of NAND: also can express any Boolean func 13
Representation: Schematic ã “Schematic” is short for “schematic diagram” l Simply means a drawing showing gates (or more complex modules) and wire connections l More complex modules are usually shown as black boxes 14
Representation: Boolean Algebra ã More on this next class 15
Representation: Truth Table ã 2 n rows: where n is # of variables 16
Schematic Diagrams ã Can you design an entire processor that way? l Yes, but diagrams are overly complex and hard to enter ã These days people prefer textual descriptions l You can call it “code, ” but it is not software! l More precisely, it is a hardware “description” 17
Hardware Description Languages ã Main ones are Verilog and VHDL l Others: Abel, System. C, Handel ã Origins as testing languages l To generate sets of input values ã Levels of use from very detailed to more abstract descriptions of hardware 18
Design w/ HDL ã Two leading HDLs: l Verilog Ø developed in 1984 by Gateway Design Automation Ø became an IEEE standard (1364) in 1995 Ø evolved into System. Verilog in 2002 l VHDL Ø Developed in 1981 by the Department of Defense Ø Became an IEEE standard (1076) in 1987 ã Most (all? ) commercial designs built using HDLs ã We will use Verilog/System. Verilog 19
Uses of HDL ã Simulation l Defines input values applied to the circuit l Outputs checked for correctness l Millions of dollars saved by debugging in simulation instead of hardware ã Synthesis l Transforms HDL spec into a circuit-level implementation Ø HDL is transformed into a “netlist” Ø “Netlist” = a list of gates and the wires connecting them – Just a textual description instead of drawing IMPORTANT: l When describing circuits using an HDL, it is critical to think of the hardware the specification should produce. 20
Verilog Module ã “Code” always organized in modules l remember: this is not really “code”, but a description of the hardware or hardware’s behavior ã Represent a logic “box” l With inputs and outputs 21
Example module example(input output *** HDL DESCRIPTION endmodule wire HERE a, b, c, y); *** 22
Levels of Verilog Several different levels (or “views”) l Mainly two types: Structural or Behavioral l Structural: Describe the physical structure of the hardware Ø Typically, gates/modules and wires that connect them l Behavioral: Describes the algorithmic behavior of the hardware Ø E. g. , Output X = Y + Z 23
Example 1 ã Output is 1 when input < 011 l Figure (b) is called a “Karnaugh Map” (or “K-Map”) Ø graphical representation of truth table: n-dimensional “cube” l Figure (c) is a “sum-of-products” implementation Ø AND-OR, implemented as NAND-NAND 24
Structural Verilog ã Explicit description of gates and connections l Textual form of schematic l Specifying “netlist” Ø netlist = gates/modules and their wire connections 25
Example 1 in Structural Verilog module example_1( input wire X, input wire Y, input wire Z, output wire F ); Can also be written as: input wire X, Y, Z, output wire F wire X_n, Y_n, Z_n, f 1, f 2; not g 0(X_n, X), g 1(Y_n, Y), g 2(Z_n, Z); nand g 3(f 1, X_n, Y_n), g 4(f 2, X_n, Z_n), g 5(F, f 1, f 2); endmodule f 1 X_n Y_n X_n f 2 actually, just a NAND gate 26
Slight Variation – Gates not named module example_1( input wire X, input wire Y, input wire Z, output wire F ); wire X_n, Y_n, Z_n, f 1, f 2; not(X_n, X); not(Y_n, Y); not(Z_n, Z); nand(f 1, X_n, Y_n); nand(f 2, X_n, Z_n); nand(F, f 1, f 2); Observe two orthogonal changes: • each gate is declared using a separate “not” or “nand” declaration • gate instances are not named endmodule 27
Explanation ã Each of these gates is an instance l Like object vs class ã In first example, they had names not g 0(X_n, X), ã In second example, no name not(X_n, X); ã Why can naming an instance be useful? 28
Gates ã Standard set of gates available l and, or, not l nand, nor l xor, xnor l buf 29
Dataflow Description (Behavioral) module example_1( ã Basically a input wire X, Y, Z, logical output wire F expression ); assign F = (~X & ~Y) | (~X & ~Z); endmodule ã No explicit gates rewritten using “sum-of-products” (AND-OR) style 30
Conditional Expressions ã Useful for: l describing multiplexers l combinational logic in an if-then-else style ã Example: Output 1 if input is less than 3 module example_2( input wire[2: 0] A, output wire F ); Notice alternate specification // A is a 3 -bit number assign F = (A < 3) ? 1 : 0; // or assign F = (A<3); endmodule 31
Abstraction ã Using the digital abstraction we have been thinking of the inputs and outputs as l True or False l 1 or 0 ã What are they really? 32
Logic Levels ã Define discrete voltages to represent 1 and 0 ã For example, we could define: l 0 to be ground or 0 volts l 1 to be VDD or 5 volts ã What about 4. 99 volts? Is that a 0 or a 1? ã What about 3. 2 volts? 33
Logic Levels ã Define a range of voltages to represent 1 and 0 ã Define different ranges for outputs and inputs to allow for noise in the system ã What is noise? 34
What is Noise? ã Anything that degrades the signal l E. g. , resistance, power supply noise, coupling to neighboring wires, etc. ã Example: a gate (driver) could output a 5 volt signal but, because of resistance in a long wire, the signal could arrive at the receiver with a degraded value, for example, 4. 5 volts 35
The Static Discipline ã Given logically valid inputs, every circuit element must produce logically valid outputs ã Discipline ourselves to use limited ranges of voltages to represent discrete values 36
Logic Levels NMH = VOH – VIH NML = VIL – VOL 37
DC Transfer Characteristics (See textbook for characteristics of an inverter) Ideal Buffer: NMH = NML = VDD/2 Real Buffer: NMH , NML < VDD/2 38
VDD Scaling ã Chips in the 1970 s and 1980 s were designed using VDD = 5 V ã As technology improved, VDD dropped l Avoid frying tiny transistors l Save power ã 3. 3 V, 2. 5 V, 1. 8 V, 1. 5 V, 1. 2 V, 1. 0 V, … 39
Logic Family Examples Logic Family VDD VIL VIH VOL VOH TTL 5 (4. 75 - 5. 25) 0. 8 2. 0 0. 4 2. 4 CMOS 5 (4. 5 - 6) 1. 35 3. 15 0. 33 3. 84 LVTTL 3. 3 (3 - 3. 6) 0. 8 2. 0 0. 4 2. 4 LVCMOS 3. 3 (3 - 3. 6) 0. 9 1. 8 0. 36 2. 7 ã LVCMOS = Low-Voltage CMOS (3. 3 V) ã AUCMOS = Advanced-Ultralow-voltage CMOS (1. 8 V) ã Today: 1. 0 -1. 2 V supply voltage is common 40
Next Class ã Boolean Algebra ã Synthesis of combinational logic 41
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