COMP 206 Computer Architecture and Implementation Montek Singh

COMP 206: Computer Architecture and Implementation Montek Singh Wed. , Oct. 6, 2004 Topic: Instruction-Level Parallelism (Dynamic Scheduling: Tomasulo’s Algorithm) 1

Reading ã Chapter 3: ILP and Its Dynamic Exploitation l Section 3. 1 -3. 3 2

Dynamic Scheduling: Tomasulo’s Algorithm ã For IBM 360/91 (about three years after CDC 6600) ã Goal: High performance without special compilers ã Differences between IBM 360 and CDC 6600 ISA l IBM has only 2 register specifiers/instruction versus 3 in CDC 6600 l IBM has 4 FP registers versus 8 in CDC 6600 ã Differences between Tomasulo Algorithm and Scoreboard l Control and buffers distributed with Function Units versus centralized in scoreboard; called “reservation stations” l Registers in instructions replaced by pointers to reservation station buffer l Hardware renaming of registers to avoid WAR and WAW hazards l Common Data Bus broadcasts results to all FUs (forwarding) l Load and Stores treated as FUs as well 3

Tomasulo: Organization From memory 1 2 3 4 5 6 Floating point operand stack Decoder Status From I-Fetch Busy bit To memory Tag Tags Addr Data FP registers (4) To all tags 10 Tag 11 Tag 12 Tag Data Tag Tag Data Adder (2 cycle, pipelined) Data Tag Data 8 Tag Data 9 Tag Multiply (3 cycle, pipelined) Divide (12 cycle, not pipelined) Common data bus (CDB) 4

More Details of Tomasulo Organization ã Entities that produce values are assigned 4 -bit tags l 1, 2, 3, 4, 5, 6 for load buffers l 8, 9 for multiplier reservation stations l 10, 11, 12 for adder reservation stations l Tag 0 indicates presence of valid data ã FP registers have “busy bits” l 0 means that register holds valid data l 1 means that it is waiting to receive value from source identified by its tag field 5

Tomasulo: Representing Data Dependences ã Inputs l Operand is a register with busy bit = 0 Ø Data copied immediately (through register bus) into reservation station Ø Tag field of RS set to 0 l Operand is a register with busy bit = 1 Ø Tag field of RS receives a copy of the register tag field l Operand is a load buffer that contains valid data Ø Data copied into RS l Operand is a load buffer that is awaiting data Ø Tag field of RS receives tag of load buffer ã Outputs l Output is a register Ø Busy bit set to 1, tag set to RS tag l Output is a store buffer Ø Tag set to RS tag, destination address set 6

Three Stages of Tomasulo Algorithm 1. Issue: get instruction from FP operation queue If reservation station free, the scoreboard issues instruction and sends operands (renames registers) 2. Execution: operate on operands (EX) When both operands ready then execute; if not ready, watch CDB for result 3. Write Result: finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available 7

Load Buffer Tomasulo: State Transitions Register • In case of a CDB conflict, earlier instruction has priority • If more than one instruction is enabled in the reservation stations of adder or multiplier in same cycle, top entry has priority • If CDB transfer and issue occur in same cycle, CDB transfer is assumed to occur first • Every instruction should spend at least one cycle in R stage • If an instruction being issued both reads and writes the same register, and the source operand is actually in the register (busy bit = 0), then first the register is read, and then its busy bit is turned to 1, making it unreadable 8

Tomasulo: Example 100: 101: 102: 103: 104: 105: 106: F 0 A F 0 F 2 F 1 C F 1 F 0 F 1 100 + + + * F 1 B F 3 F 2 / F 0 101 I R X W Issued In reservation station 102 In execution Writing result through CDB 103 104 106 105 9

Tomasulo Example Cycle 0 ã System is quiescent 10

Tomasulo Example Cycle 1 ã (A) will arrive at tag 4 ã (F 0) will come from tag 4 ã F 0 is set to “busy” 11

Tomasulo Example Cycle 2 ã (F 0) will be produced at tag 10 ã Right input of adder came from register (tag bit = 0) ã Left input of adder will come from tag 4 ã Forwarding tag of F 0 has been changed from 4 to 10 12

Tomasulo Example Cycle 3 ã (F 0) will be produced at tag 11 ã (B) will arrive at tag 3 ã Right input of adder will come from tag 3 ã Left input of adder will come from tag 10 ã (A) arrives from memory ã Forwarding tag of F 0 has been changed from 10 to 11 13

Tomasulo Example Cycle 4 ã (F 2) will be produced at tag 12 ã Right input of adder came from register (tag bit = 0) ã Left input of adder came from register (tag bit = 0) ã (A) with tag 4 is broadcast on CDB ã Adder (at tag 10) picks it up, and is thereby enabled ã The instruction that will write F 2 has already read the old contents of F 2 14

Tomasulo Example Cycle 5 ã (F 1) will be produced at tag 8 ã Right input of multiplier will come from tag 12 ã Left input of multiplier came from register (tag bit = 0) ã Adder (at tag 10) starts computing ã (B) arrives from memory 15

Tomasulo Example Cycle 6 ã Memory address of destination is C ã Data will come from tag 8 ã Adder (at tag 10) finishes computing ã (B) with tag 3 is broadcast on CDB ã Adder (at tag 11) picks it up ã Adder (at tag 12) starts computing 16

Tomasulo Example Cycle 7 ã (F 1) will be produced at tag 9 ã Right input of divider will come from tag 11 ã Left input of divider will come from tag 8 ã Result of adder (with tag 10) is broadcast on CDB ã Adder (at tag 11) picks it up and is thereby enabled ã Adder (at tag 12) finishes computing 17

Tomasulo Example Cycle 8 ã Result of adder (at tag 12) is broadcast on CDB ã Multiplier (at tag 12) picks it up and is thereby enabled 18

Tomasulo Example Cycle 9 ã Multiplier (at tag 8) starts computing ã Adder (at tag 11) finishes computing 19

Tomasulo Example Cycle 10 ã Result of adder (with tag 11) is broadcast on CDB ã Divider (at tag 9) picks it up ã Register F 0 picks it up 20

Tomasulo Example Cycle 11 ã Multiplier (at tag 8) finishes computing 21

Tomasulo Example Cycle 12 ã Result of multiplier (at tag 8) is broadcast on CDB ã Divider (at tag 9) picks it up, and is thereby enabled ã Store buffer (at tag 1) picks it up, and is thereby enabled 22

Observations on Tomasulo’s Algorithm ã Instructions: move from decoder to reservation stations l in program order l dependences can be correctly recorded ã Data Flow Graph: The graph of pointers connecting the RS, registers, and memory buffers l helps accomplish out-of-order sequencing of instructions ã Chief cost of this scheme: high-speed associative hardware l RS hardware has to search for tags when CDB broadcasts some value with its tag ã Full load bypassing is supported l load and store buffers are treated just like functional units l additional hardware on 360/91 also supported load forwarding 23

Tomasulo: Example of Load Bypassing ã Instruction 202 depends on 200: 201: 202: 203: 204: F 0 A F 0 / F 1 C F 0 D F 0 * F 2 instructions 200 and 201, so instruction 203 will start executing much before 202 (assuming C and D are found to be different memory addresses) ã Work out details off-line 24

Tomasulo: “Loop Unrolling in Hardware” ã 360/91 supported limited kind of speculation l Small loops could be held in a loop buffer l Loop closing branches were predicted as taken ã This has the effect of loop unrolling at run-time l Given the small number of FP registers in machine, software loop unrolling was not a viable option 25

Tomasulo Loop Example Loop: L. D MULT. D SUBI BNEZ F 0 F 4 R 1 0 F 0 0 R 1 Loop R 1 F 2 R 1 #8 ã Multiply takes 4 clocks ã Loads have cache misses 26

Loop Example Cycle 0 27

Loop Example Cycle 1 28

Loop Example Cycle 2 29

Loop Example Cycle 3 30

Loop Example Cycle 4 31

Loop Example Cycle 5 32

Loop Example Cycle 6 Load 2 33

Loop Example Cycle 7 34

Loop Example Cycle 8 35

Loop Example Cycle 9 36

Loop Example Cycle 10 37

Loop Example Cycle 11 38

Loop Example Cycle 12 39

Loop Example Cycle 13 40

Loop Example Cycle 14 41

Loop Example Cycle 15 42

Loop Example Cycle 16 43

Loop Example Cycle 17 44

Loop Example Cycle 18 45

Loop Example Cycle 19 46

Loop Example Cycle 20 47

Loop Example Cycle 21 48

Summary of Tomasulo’s Algorithm ã Prevents registers as bottleneck ã Avoids WAR and WAW hazards of scoreboard ã Allows loop unrolling in hardware ã Not limited to basic blocks (provided we have branch prediction) ã Lasting contributions l Dynamic scheduling l Register renaming l Load/store disambiguation ã Next: Dynamic branch prediction 49