Basic Computer Organization Design 1 BASIC COMPUTER ORGANIZATION

Basic Computer Organization & Design 1 BASIC COMPUTER ORGANIZATION AND DESIGN • Instruction Codes • Computer Registers • Computer Instructions • Timing and Control • Instruction Cycle • Memory Reference Instructions • Input-Output and Interrupt • Complete Computer Description • Design of Basic Computer • Design of Accumulator Logic Computer Organization Computer Architectures

Basic Computer Organization & Design 2 INTRODUCTION • Every different processor type has its own design (different registers, buses, microoperations, machine instructions, etc) • Modern processors are very complex devices. • It contains – Many registers – Multiple arithmetic units, for both integer and floating point calculations – The ability to pipeline several consecutive instructions to speed execution – Etc. Computer Organization Computer Architectures

Basic Computer Organization & Design 3 INTRODUCTION • However, to understand how processors work, we will start with a simplified processor model. • M. Morris Mano introduces a simple processor model he calls the “Basic Computer” • We will use this to introduce processor organization and the relationship of the RTL model to the higher level computer processor. Computer Organization Computer Architectures

Basic Computer Organization & Design 4 THE BASIC COMPUTER • The Basic Computer has two components, - a processor - and memory • The memory has 4096 words in it (for this chapter) 4096 = 212, RAM CPU so it takes 12 bits address to select a word in memory. • Each word is 16 bits long. 0 15 0 4095 Computer Organization Computer Architectures

Basic Computer Organization & Design 5 Instruction codes INSTRUCTIONS • Program – A sequence instructions. of (machine) • (Machine) Instruction – A group of bits that tell the computer to perform a specific operation (a sequence of microoperation). Computer Organization Computer Architectures

Basic Computer Organization & Design 6 Instruction codes INSTRUCTIONS • The instructions of a program, along with any needed data are stored in memory. • The CPU reads the next instruction from memory. (by using PC and AR) • It is placed in an Instruction Register (IR). • Control circuitry in control unit then translates the instruction into the sequence of microoperations necessary to implement it. Computer Organization Computer Architectures

Basic Computer Organization & Design 7 Instruction codes INSTRUCTION FORMAT • A computer instruction is often divided into two parts –An opcode (Operation Code) part that specifies the operation for that instruction –An address part that specifies the registers and/or locations in memory to use for that operation • In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12 bit to specify which memory address this instruction will use (0 -11 bits). Computer Organization Computer Architectures

Basic Computer Organization & Design 8 Instruction codes INSTRUCTION FORMAT • In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0: direct addressing, 1: indirect addressing) • Since the memory words, and hence the instructions, are 16 bits long, that leaves 3 bits for the instruction’s opcode (12 -14 bits) Instruction Format 15 14 12 11 Opcode I 0 Addressing mode Computer Organization Computer Architectures

Basic Computer Organization & Design 9 Instruction codes ADDRESSING MODES • The address field of an instruction can represent either : –Direct address (0 bit in the addressing mode field): the address in memory of the data to use (the address of the operand), or –Indirect address (1 bit in the addressing mode field): the address in memory of the data to use [When the second part of an instruction code specifies an operand, the instruction is said to have an immediate operand. ] Computer Organization Computer Architectures

Basic Computer Organization & Design 10 Instruction codes ADDRESSING MODES Indirect addressing Direct addressing 22 0 ADD 457 35 300 457 1 ADD 300 1350 Operand 1350 + AC Operand + AC Effective Address (EA) - The address, that can be directly used without modification to access an operand for a computation-type instruction, or as the target address for a branch-type instruction (457 in Direct address, 1350 in indirect ) Computer Organization Computer Architectures

Basic Computer Organization & Design 11 Instruction codes PROCESSOR REGISTERS • A processor has many registers to hold instructions, addresses, data, etc. • The processor has a register, the Program Counter (PC) that holds the memory address of the next instruction to get. –Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bits. Computer Organization Computer Architectures

Basic Computer Organization & Design 12 Instruction codes PROCESSOR REGISTERS • In a direct or indirect addressing, the processor needs to keep track of what locations in memory it is addressing: The Address Register (AR) is used for this. –The AR is a 12 bit register in the Basic Computer. • When an operand is found, using either direct or indirect addressing, it is placed in the Data Register (DR). The processor then uses this value as data for its operation. Computer Organization Computer Architectures

Basic Computer Organization & Design 13 Instruction codes PROCESSOR REGISTERS • The Basic Computer has a single general purpose register – the Accumulator (AC). • The significance of a general purpose register is that it can be referred to in instructions. – e. g. load AC with the contents of a specific memory location; store the contents of AC into a specified memory location • Often a processor will need a register to store intermediate results or other temporary data; in the Basic Computer this is the Temporary Register (TR). Computer Organization Computer Architectures

Basic Computer Organization & Design 14 Instruction codes PROCESSOR REGISTERS • The Basic Computer uses a very simple model of input/output (I/O) operations –Input devices are considered to send 8 bits of character data to the processor –The processor can send 8 bits of character data to output devices • The Input Register (INPR) holds an 8 bit character gotten from an input device • The Output Register (OUTR) holds an 8 bit character to be send to an output device Computer Organization Computer Architectures

Basic Computer Organization & Design 15 Registers BASIC COMPUTER REGISTERS Registers in the Basic Computer 11 0 PC Memory 11 0 4096 x 16 AR 15 0 IR CPU 15 0 15 TR 7 0 OUTR 0 DR 7 0 15 INPR 0 AC List of Basic Computer Registers DR AR AC IR PC TR INPR OUTR 16 12 16 8 8 Computer Organization Data Register Address Register Accumulator Instruction Register Program Counter Temporary Register Input Register Output Register Holds memory operand Holds address for memory Processor register Holds instruction code Holds address of instruction Holds temporary data Holds input character Holds output character Computer Architectures

Basic Computer Organization & Design 16 Registers COMMON BUS SYSTEM The basic computer has eight registers, a memory unit, and a control unit. Paths must be provided to transfer information from one register to another and between memory and register. The registers in the Basic Computer are connected using a common bus (as in ch. 4). • This gives a savings in circuitry over complete connections between registers. Computer Organization Computer Architectures

Basic Computer Organization & Design 17 Registers COMMON BUS SYSTEM S 2 S 1 S 0 Register 0 0 1 1 0 1 0 1 Memory unit 4096 x 16 x AR PC DR AC IR TR Memory Write Bus 7 Address Read AR 1 LD INR CLR PC 2 LD INR CLR DR 3 LD INR CLR E AC ALU 4 LD INR CLR INPR IR 5 TR 6 LD LD INR CLR OUTR LD 16 -bit common bus Computer Organization Clock Outputs of the six registers and memory unit are connected to the common bus of 16 lines. The specific output is selected from the binary value of the selection variables S 2, S 1, S 0. The lines from the common bus are connected to the inputs of each register and the data input of the memory. The particular register whose LD (Load) input is enabled receives the data from the bus. INPR receives the a character from an input device and which is then transferred to AC. OUTR receive the character from AC and delivers it to an output device. Computer Architectures

Basic Computer Organization & Design 18 Registers COMMON BUS SYSTEM Read Memory 4096 x 16 INPR Write E Address ALU S 2 S 1 S 0 0 0 1 1 AC L I L I C C C L DR IR L I 1 x AR PC DR AC IR TR Memory C OUTR AR 7 0 1 0 1 TR PC L I 0 0 1 1 Register LD C 2 3 4 5 6 16 -bit Common Bus S 0 S 1 S 2 Computer Organization Computer Architectures

Basic Computer Organization & Design 19 Registers COMMON BUS SYSTEM • Three control lines, S 2, S 1, and S 0 control which register the bus selects as its input. Either one of the registers will S S S Register 0 0 0 x have its load signal activated, 0 0 1 AR 0 1 0 PC or the memory will have its 0 1 1 DR 1 0 0 AC write signal activated. 1 0 1 IR 1 1 0 TR 1 1 1 Memory - Will determine where the data from the bus gets loaded. • The 12 -bit registers, AR and PC, have 0’s onto the bus in the high order 4 bit positions. • When the 8 -bit register OUTR is loaded from the bus, the data comes from the low order 8 bits on the bus. 2 1 Computer Organization 0 Computer Architectures

Basic Computer Organization & Design 20 Instructions BASIC COMPUTER INSTRUCTIONS • The basic computer has three instruction code formats. Each format has 16 bits. Memory-Reference Instructions (OP-code = 000 ~ 110) 15 I 14 12 11 Opcode 0 Address Register-Reference Instructions (OP-code = 111, I = 0) 15 0 1 1 12 11 Register operation 1 0 Input-Output Instructions (OP-code =111, I = 1) 15 1 1 Computer Organization 12 11 1 1 0 I/O operation Computer Architectures

Basic Computer Organization & Design 21 Instructions BASIC COMPUTER INSTRUCTIONS Binary Hexa. Description AND memory word to AC Add memory word to AC Load AC from memory Store content of AC into memory Branch unconditionally Branch and save return address Increment and skip if zero 0000 0 0001 1 0010 2 0011 3 0100 4 7800 7400 7200 7100 7080 7040 7020 7010 7008 7004 7002 7001 Clear AC Clear E Complement AC Complement E Circulate right AC and E Circulate left AC and E Increment AC Skip next instr. if AC is positive Skip next instr. if AC is negative Skip next instr. if AC is zero Skip next instr. if E is zero Halt computer 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B F 800 F 400 F 200 F 100 F 080 F 040 Input character to AC Output character from AC Skip on input flag Skip on output flag Interrupt on Interrupt off 1100 C 1101 D 1110 E 1111 F Hex Code I=0 I=1 0 xxx 8 xxx 1 xxx 9 xxx 2 xxx Axxx 3 xxx Bxxx 4 xxx Cxxx 5 xxx Dxxx 6 xxx Exxx CLA CLE CMA CME CIR CIL INC SPA SNA SZE HLT INP OUT SKI SKO ION IOF Symbol AND ADD LDA STA BUN BSA ISZ Computer Organization Computer Architectures

Basic Computer Organization & Design 22 Instructions INSTRUCTION SET COMPLETENESS A computer should have a set of instructions so that the user can construct machine language programs to evaluate any function that is known to be computable. • Instruction Types Functional Instructions - Arithmetic, logic, and shift instructions - ADD, CMA, INC, CIR, CIL, AND, CLA Transfer Instructions - Data transfers between the main memory and the processor registers - LDA, STA Control Instructions - Program sequencing and control - BUN, BSA, ISZ Input/Output Instructions - Input and output - INP, OUT Computer Organization Computer Architectures

Basic Computer Organization & Design 23 Instruction codes TIMING AND CONTROL The timing for all registers in the basic computer is controlled by a master clock generator. The clock pulses are applied to all F-F and registers in the system, including the F-F and registers in the control unit. • Control unit (CU) of a processor translates from machine instructions to the control signals for the microoperations that implement them. Computer Organization Computer Architectures

Basic Computer Organization & Design 24 Instruction codes TIMING AND CONTROL • Control units (CU) are implemented in one of two ways • Hardwired Control - CU is made up of sequential and combinational circuits to generate the control signals • Microprogrammed Control - A control memory on the processor contains microprograms that activate the necessary control signals • We will consider a hardwired implementation of the control unit for the Basic Computer Organization Computer Architectures

Basic Computer Organization & Design 25 Timing and control TIMING AND CONTROL Control unit of Basic Computer 15 Instruction register (IR) 14 13 12 11 - 0 Other inputs T 0 : AR PC specifies a transfer of the content of PC into AR if timing signal T 0 is active. 3 x 8 decoder 7 6543 210 D 0 I D 7 Combinational Control logic The output of the counter are decoded by 4 x 16 decoder in to 16 timing signals T 0 – T 15. e. g. T 15 T 0 15 14. . 2 1 0 4 x 16 decoder 4 -bit sequence counter (SC) Computer Organization Control signals D 3 T 4 : SC Increment (INR) Clear (CLR) Clock 0 This means at T 4, SC is cleared to 0 if decoder output D 3 is active. Computer Architectures

Basic Computer Organization & Design 26 Timing and control TIMING SIGNALS - Generated by 4 -bit sequence counter and 4 16 decoder -The SC can be incremented or cleared. -- Example: T 0, T 1, T 2, T 3, T 4, T 0, T 1, . . . Assume: At time T 4, SC is cleared to 0 if decoder output D 3 is active. D T : SC 0 3 4 Computer Organization Computer Architectures

Basic Computer Organization & Design 27 INSTRUCTION CYCLE • In Basic Computer, a machine instruction is consists in the following phases: 1. Fetch an instruction from memory (T 0) 2. Decode the instruction (T 1) 3. Read the effective address from memory if the instruction has an indirect address (T 2) 4. Execute the instruction (T 3) • After an instruction is executed, the cycle starts again at step 1, for the next instruction. This process continues indefinitely unless a HALT instruction is encountered. • Note: Every different processor has its own (different) instruction cycle Computer Organization Computer Architectures

Basic Computer Organization & Design 28 Instruction Cycle FETCH and DECODE • Fetch and Decode T 0: AR PC (S 0 S 1 S 2=010, T 0=1) T 1: IR M [AR], PC + 1 (S 0 S 1 S 2=111, T 1=1) T 2: D 0, . . . , D 7 Decode IR(12 -14), AR IR(0 -11), I IR(15) T 1 S 2 T 0 S 1 Bus S 0 Memory unit 7 Address Read AR 1 LD PC 2 INR IR LD Common bus Computer Organization 5 Clock Initially, the program counter PC is loaded with the address of the first instruction in the program. The Sequence counter SC is cleared to 0, providing a decoded timing signal T 0. After each clock pulse, SC is incremented by one, so that the timing signal go through a sequence T 0, T 1, T 2 and so on. Computer Architectures

Basic Computer Organization & Design 29 Instrction Cycle DETERMINE THE TYPE OF INSTRUCTION Start SC 0 AR PC Decoder output D 7 is equal to 1 if the operation code is equal to the binary 111. T 0 IR M[AR], PC + 1 T 2 Decode Opcode in IR(12 -14), AR IR(0 -11), I IR(15) (Register or I/O) = 1 D 7 (I/O) = 1 I T 3 Execute input-output instruction SC 0 D'7 IT 3: D'7 I’T 3: D 7 IT 3: = 0 (Memory-reference) = 0 (register) (indirect) = 1 T 3 Execute register-reference instruction SC 0 T 3 AR M[AR] I = 0 (direct) T 3 Nothing Execute memory-reference instruction SC 0 T 4 AR M[AR] Nothing Execute a register-reference instruction. Execute an input-output instruction. Computer Organization Computer Architectures

Basic Computer Organization & Design 30 Instruction Cycle REGISTER REFERENCE INSTRUCTIONS Register Reference Instructions are identified when - D 7 = 1 and I = 0 - These instruction use bits 0 through 11 of the instruction code to specify one of the 12 instructions. These 12 bits are available in b 0 ~ b 11 of IR - Execution starts with timing signal T 3 r = D 7 I T 3 => common to all Register Reference Instruction Bi = IR(i) , i=0, 1, 2, . . . , 11 => bits in IR(0 -11) that specifies the operation CLA CLE CMA CME CIR CIL INC SPA SNA SZE HLT r: r. B 11: r. B 10: r. B 9: r. B 8: r. B 7: r. B 6: r. B 5: r. B 4: r. B 3: r. B 2: r. B 1: r. B 0: Computer Organization Hex 7800 7400 7200 7100 7080 7040 7020 7010 7008 7004 7002 7001 SC 0 Clear SC AC 0 Clear AC E 0 Clear E AC AC’ Comp. AC E E’ Comp. E AC shr AC, AC(15) E, E AC(0) Circulate right AC shl AC, AC(0) E, E AC(15) Circu. Left AC + 1 Increment AC if (AC(15) = 0) then (PC PC+1) skip if positive if (AC(15) = 1) then (PC PC+1) skip if negative if (AC = 0) then (PC PC+1) skip if AC zero if (E = 0) then (PC PC+1) skip if E zero S 0 (S is a start-stop flip-flop) Halt computer Computer Architectures

Basic Computer Organization & Design 31 MR Instructions MEMORY REFERENCE INSTRUCTIONS Symbol AND ADD LDA STA BUN BSA ISZ Operation Decoder D 0 D 1 D 2 D 3 D 4 D 5 D 6 Symbolic Description AC M[AR] AC + M[AR], E Cout AC M[AR] AC PC AR M[AR] PC, PC AR + 1 M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1 - The effective address of the instruction is in AR and was placed there during timing signal T 2 when I = 0, or during timing signal T 3 when I = 1 - Memory cycle is assumed to be short enough to complete in a CPU cycle - The execution of memory reference instruction starts with T 4 AND to AC D 0 T 4 : D 0 T 5 : ADD to AC D 1 T 4 : D 1 T 5 : DR M[AR] AC DR, SC 0 Read operand AND with AC DR M[AR] AC + DR, E Cout, SC 0 Read operand Add to AC and store carry in E Computer Organization Computer Architectures

Basic Computer Organization & Design 32 MEMORY REFERENCE INSTRUCTIONS LDA: Load to AC D 2 T 4: DR M[AR] D 2 T 5: AC DR, SC 0 STA: Store AC D 3 T 4: M[AR] AC, SC 0 BUN: Branch Unconditionally (transfer the program to the instruction specified by the effective address) D 4 T 4: PC AR, SC 0 BSA: Branch and Save Return Address (useful in subroutine or procedure) M[AR] PC, PC AR + 1 Memory, PC, AR at time T 4 20 PC = 21 0 BSA 135 Next instruction AR = 135 136 Subroutine 1 BUN Memory Computer Organization 135 Memory, PC after execution 20 0 BSA 135 21 Next instruction 135 21 Subroutine PC = 136 1 BUN 135 Memory Computer Architectures

Basic Computer Organization & Design 33 MR Instructions MEMORY REFERENCE INSTRUCTIONS BSA (Contd. ): It is not possible to perform the operation of the BSA instruction in one clock cycle when we use the bus system of the basic computer. To use the memory and the bus properly, the BSA instruction must be executed with a sequence of two microoperations : D 5 T 4: M[AR] PC, AR + 1 D 5 T 5: PC AR, SC 0 ISZ (Increment and Skip-if-Zero): This instruction increment the word specified by the effective address, and if the incremented value is equal to 0, PC is incremented by 1. D 6 T 4: DR M[AR] D 6 T 5: DR + 1 D 6 T 4: M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0 Computer Organization Computer Architectures

Basic Computer Organization & Design 34 MR Instructions FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS Memory-reference instruction AND D 0 T 4 DR M[AR] ADD LDA D 1 T 4 DR M[AR] D 0 T 5 D 1 T 5 AC DR AC + DR SC 0 E Cout SC 0 BUN BSA STA D 2 T 4 DR M[AR] D 3 T 4 M[AR] AC SC 0 D 2 T 5 AC DR SC 0 ISZ D 4 T 4 D 5 T 4 D 6 T 4 PC AR M[AR] PC DR M[AR] SC 0 AR + 1 D 5 T 5 PC AR SC 0 D 6 T 5 DR + 1 D 6 T 6 M[AR] DR If (DR = 0) then (PC PC + 1) SC 0 Computer Organization Computer Architectures

Basic Computer Organization & Design 35 I/O and Interrupt INPUT-OUTPUT AND INTERRUPT A Terminal with a keyboard and a Printer • Input-Output Configuration INPR OUTR FGI FGO IEN Input register - 8 bits Output register - 8 bits Input flag - 1 bit Output flag - 1 bit Interrupt enable - 1 bit Input-output terminal Printer Serial communication interface Receiver interface Computer registers and flip-flops OUTR FGO IEN AC Keyboard Parallel Communications Path Transmitter interface INPR FGI Serial Communications Path -The terminal sends and receives serial information (Each info 8 bits code) -The serial info. from the keyboard is transferred into INPR -The serial info. for the printer is stored in the OUTR Computer Organization Computer Architectures

Basic Computer Organization & Design • • 36 INPUT-OUTPUT AND INTERRUPT INPR and OUTR communicate with the terminal serially and with the AC in parallel. The flags are needed to synchronize the timing difference between I/O device and the computer The FGI is set to 1 when new info. is available in input device and is cleared when info. is accepted by the computer. For output – Initially FGO is set to 1. If FGO=1 the computer transfer info. AC to OUTR and set FGO to 0. The output device accepts the info. and set FGO to 1. Computer Organization Computer Architectures

Basic Computer Organization & Design 37 I/O and Interrupt PROGRAM CONTROLLED DATA TRANSFER -- CPU -- -- I/O Device -- /* Input */ /* Initially FGI = 0 */ loop: If FGI = 0 goto loop AC INPR, FGI 0 loop: If FGI = 1 goto loop /* Output */ /* Initially FGO = 1 */ loop: If FGO = 1 goto loop OUTR AC, FGO 0 loop: If FGO = 0 goto loop INPR new data, FGI 1 consume OUTR, FGO 1 FGI=0 FGO=1 Start Input Start Output FGI 0 yes FGI=0 AC Data yes no no AC INPR yes More Character no END Computer Organization FGO=1 OUTR AC FGO 1 yes More Character no END Computer Architectures

Basic Computer Organization & Design 38 INPUT-OUTPUT INSTRUCTIONS D 7 IT 3 = p IR(i) = Bi, i = 6, …, 11 p: INP p. B 11: OUT p. B 10: SKI p. B 9: SKO p. B 8: ION p. B 7: IOF p. B 6: SC 0 AC(0 -7) INPR, FGI 0 OUTR AC(0 -7), FGO 0 if(FGI = 1) then (PC PC + 1) if(FGO = 1) then (PC PC + 1) IEN 1 IEN 0 Computer Organization Clear SC Input char. to AC Output char. from AC Skip on input flag Skip on output flag Interrupt enable on Interrupt enable off Computer Architectures

Basic Computer Organization & Design 39 INTERRUPT INITIATED INPUT/OUTPUT -Open communication only when some data has to be passed --> interrupt. -The I/O interface, instead of the CPU, monitors the I/O device. -When the interface founds that the I/O device is ready for data transfer, it generates an interrupt request to the CPU. Computer Organization Computer Architectures

Basic Computer Organization & Design 40 INTERRUPT INITIATED INPUT/OUTPUT -Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing. * IEN (Interrupt-enable flip-flop) - can be set and cleared by instructions - when cleared (=0), the computer cannot be interrupted. Computer Organization Computer Architectures

Basic Computer Organization & Design 41 I/O and Interrupt FLOWCHART FOR INTERRUPT CYCLE R = Interrupt f/f Instruction cycle =0 IEN =1 =1 =1 R 1 FGI =0 FGO =0 =1 Interrupt cycle Store return address in location 0 M[0] PC Fetch and decode instructions Execute instructions R =0 Branch to location 1 PC 1 IEN 0 R 0 If IEN is 0 , it indicates that the programmer does not want to use the interrupt, If IEN is 1, control checks the flag bit, if both flag bits are 0 , it indicates the input/output registers are not ready. If any flag bit is 1 while IEN=1, flip-flop R is set to 1. -The interrupt cycle is a HW implementation of a branch and save return address operation. The return address available in PC is stored in a specific location (may be a processor register, memory stack, a specific memory location) where it can be found later when the program returns to the instruction at which it was interrupted. Computer Organization Computer Architectures

Basic Computer Organization & Design 42 I/O and Interrupt REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE Memory Before interrupt 0 1 0 BUN 1120 Main Program 255 PC = 256 1120 After interrupt cycle 0 PC = 1 0 Main Program 255 256 1120 I/O Program 1 BUN 256 BUN 1120 I/O Program 0 1 BUN 0 Suppose that an interrupt occurs and R is set to 1 while the control is executing the instruction at address 255. AT this time, the return address 256 is in PC. The programmer has previously placed an input-output service program in memory starting from address 1120 and a BUN 1120 instruction at address 1 (as in first fig. ). When control finds R = 1, it proceeds with in interrupt cycle. The content of PC(256) is stored in memory location 0, PC is set to 1, and R I cleared to 0 at next cycle the next instruction is read from memory address 1. The branch instruction at address transfer the control to I/O service program at address 1120. Computer Organization Computer Architectures

Basic Computer Organization & Design 43 COMPLETE COMPUTER DESCRIPTION Description Flowchart of Operations start SC 0, IEN 0, R 0 =0(Instruction R Cycle) R’T 0 AR PC R’T 1 IR M[AR], PC + 1 R’T 2 AR IR(0~11), I IR(15) D 0. . . D 7 Decode IR(12 ~ 14) =1(Register or I/O) =1 (I/O) I D 7 IT 3 Execute I/O Instruction =0 (Register) D 7 I’T 3 Execute RR Instruction D 7 =1(Interrupt Cycle) RT 0 AR 0, TR PC RT 1 M[AR] TR, PC 0 RT 2 PC + 1, IEN 0 R 0, SC 0 =0(Memory Ref) =1(Indir) D 7’IT 3 AR <- M[AR] I =0(Dir) D 7’I’T 3 Idle Execute MR Instruction Computer Organization D 7’T 4 Computer Architectures

Basic Computer Organization & Design 44 Description Control Function and Microoperations for the Basic Computer Fetch Decode R T 0: R T 1: R T 2: Indirect D 7 IT 3: Interrupt T 0 T 1 T 2 (IEN)(FGI + FGO): RT 0: RT 1: RT 2: Memory-Reference AND D 0 T 4: D 0 T 5: ADD D 1 T 4: D 1 T 5: LDA D 2 T 4: D 2 T 5: STA D 3 T 4: BUN D 4 T 4: BSA D 5 T 4: D 5 T 5: ISZ D 6 T 4: D 6 T 5: D 6 T 6: Computer Organization AR PC IR M[AR], PC + 1 D 0, . . . , D 7 Decode IR(12 ~ 14), AR IR(0 ~ 11), I IR(15) AR M[AR] R 1 AR 0, TR PC M[AR] TR, PC 0 PC + 1, IEN 0, R 0, SC 0 DR M[AR] AC DR, SC 0 DR M[AR] AC + DR, E Cout, SC 0 DR M[AR] AC DR, SC 0 M[AR] AC, SC 0 PC AR, SC 0 M[AR] PC, AR + 1 PC AR, SC 0 DR M[AR] DR + 1 M[AR] DR, if(DR=0) then (PC PC + 1), SC 0 Computer Architectures

Basic Computer Organization & Design 45 Description COMPLETE COMPUTER DESCRIPTION Microoperations Register-Reference D 7 I T 3 = r IR(i) = Bi r: CLA r. B 11: CLE r. B 10: CMA r. B 9: CME r. B 8: CIR r. B 7: CIL r. B 6: INC r. B 5: SPA r. B 4: SNA r. B 3: SZA r. B 2: SZE r. B 1: HLT r. B 0: Input-Output INP OUT SKI SKO ION IOF Computer Organization D 7 IT 3 = p IR(i) = Bi p: p. B 11: p. B 10: p. B 9: p. B 8: p. B 7: p. B 6: (Common to all register-reference instr) (i = 0, 1, 2, . . . , 11) SC 0 AC 0 E 0 AC E E AC shr AC, AC(15) E, E AC(0) AC shl AC, AC(0) E, E AC(15) AC + 1 If(AC(15) =0) then (PC PC + 1) If(AC(15) =1) then (PC PC + 1) If(AC = 0) then (PC PC + 1) If(E=0) then (PC PC + 1) S 0 (Common to all input-output instructions) (i = 6, 7, 8, 9, 10, 11) SC 0 AC(0 -7) INPR, FGI 0 OUTR AC(0 -7), FGO 0 If(FGI=1) then (PC PC + 1) If(FGO=1) then (PC PC + 1) IEN 1 IEN 0 Computer Architectures

Basic Computer Organization & Design 46 Design of Basic Computer DESIGN OF BASIC COMPUTER(BC) Hardware Components of BC A memory unit: 4096 x 16. Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC Flip-Flops(Status): E, R, IEN, FGI, and FGO Decoders: a 3 x 8 Opcode decoder a 4 x 16 timing decoder Common bus: 16 bits Control logic gates: used in control unit Adder and Logic circuit: Connected to AC Control Logic Gates - Input Controls of the nine registers - Read and Write Controls of memory - Set, Clear, or Complement Controls of the flip-flops - S 2, S 1, S 0 Controls to select a register for the bus - AC, and Adder and Logic circuit Computer Organization Computer Architectures

Basic Computer Organization & Design 47 Design of Basic Computer CONTROL OF REGISTERS AND MEMORY Address Register; AR Scan all of the register transfer statements that change the content of AR: R’T 0: AR PC LD(AR) R’T 2: AR IR(0 -11) LD(AR) R = Interrupt Flip-Flop D’ 7 IT 3: AR M[AR] LD(AR) RT 0: AR 0 CLR(AR) D 5 T 4: AR + 1 INR(AR) LD(AR) = R’ T 0 + R’ T 2 + D'7 IT 3 CLR(AR) = RT 0 INR(AR) = D 5 T 4 D' 7 I T 2 T 3 R T 0 D 5 T 4 Computer Organization From bus 12 12 AR To bus Clock LD INR CLR Gate Structure associated with the control inputs of AR Computer Architectures

Basic Computer Organization & Design 48 Design of Basic Computer CONTROL OF COMMON BUS x 1 S x 2 x 3 Encoder x 4 S 2 1 x 5 Multiplexer bus select inputs S x 6 0 x 7 x 1 x 2 x 3 x 4 x 5 x 6 x 7 0 1 0 0 0 For AR 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 S 2 S 1 S 0 0 0 1 1 0 1 0 1 selected register none AR PC DR AC IR TR Memory D 4 T 4: PC AR D 5 T 5: PC AR x 1 = D 4 T 4 + D 5 T 5 Computer Organization Computer Architectures

Basic Computer Organization & Design 49 Design of AC Logic DESIGN OF ACCUMULATOR LOGIC Circuits associated with AC 16 16 Adder and From DR From INPR 8 logic 16 16 AC circuit To bus LD INR CLR Clock Control gates All the statements that change the content of AC D 0 T 5 : D 1 T 5 : D 2 T 5 : p. B 11: r. B 9: r. B 7 : r. B 6 : r. B 11 : r. B 5 : AC DR AC + DR AC(0 -7) INPR AC AC shr AC, AC(15) E AC shl AC, AC(0) E AC 0 AC + 1 Computer Organization AND with DR Add with DR Transfer from INPR Complement Shift right Shift left Clear Increment Computer Architectures

Basic Computer Organization & Design 50 Design of AC Logic CONTROL OF AC REGISTER Gate structures for controlling the LD, INR, and CLR of AC From Adder and Logic D 0 T 5 D 1 AND D 2 T 5 p B 11 r B 9 DR B 7 B 6 B 5 ADD 16 16 AC To bus Clock LD INR CLR INPR COM SHR SHL INC CLR B 11 Computer Organization Computer Architectures

Basic Computer Organization & Design 51 Assignment (Home Work) • List out all the microoperations for each registers and memory used in chapter 5 and draw there logic gate diagram (Gate Structure). Computer Organization Computer Architectures