State Finite State Machines Hakim Weatherspoon CS 3410

State & Finite State Machines Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H Appendix C. 7. C. 8, C. 10, C. 11

Big Picture: Building a Processor memory inst +4 register file +4 =? PC control offset new pc alu target imm cmp addr din dout memory extend A Single cycle processor 2

Stateful Components Until now is combinatorial logic • Output is computed when inputs are present • System has no internal state • Nothing computed in the present can depend on what happened in the past! Inputs N Combinational circuit M Outputs Need a way to record data Need a way to build stateful circuits Need a state-holding device Finite State Machines 3

detect How can we store and change values? B 8 Ballots (a) enc 3 7 LED decode 7 How do we create vote counter machine C (d) All the above A (b) A B Q (c) R (e) None S Q 4

Unstable Devices B C A 5

Bistable Devices • Stable and unstable equilibria? A A Simple Device B • In stable state, A = B 0 A 1 1 B A • How do we change the state? 0 B

SR Latch Q R S Q S R 0 0 0 1 1 Q Q • Set-Reset (S-R) Latch • Stores a value Q and its complement

SR Latch Q R S Q S R 0 0 0 1 1 Q Q • Set-Reset (S-R) Latch • Stores a value Q and its complement • S=1 and R=1 ?

SR Latch Q R S Q R Q S R Q Q 0 0 Q Q 0 1 0 1 1 ? ? • Set-Reset (S-R) Latch • Stores a value Q and its complement • S=1 and R=1 ?

(Unclocked) D Latch D Q D R S Q • Data (D) Latch – Easier to use than an SR latch – No possibility of entering an undefined state Q R Q D Q Q 0 1 • When D changes, Q changes § … immediately (…after a delay of 2 Ors and 2 NOTs) • Need to control when the output changes S

(Unclocked) D Latch D Q D R S Q • Data (D) Latch – Easier to use than an SR latch – No possibility of entering an undefined state Q R Q D Q Q 0 0 1 1 1 0 • When D changes, Q changes § … immediately (…after a delay of 2 Ors and 2 NOTs) • Need to control when the output changes S

Clocks • Clock helps coordinate state changes – Usually generated by an oscillating crystal – Fixed period; frequency = 1/period 1 0

Edge-triggering • Can design circuits to change on the rising or falling edge • Trigger on rising edge = positive edge-triggered • Trigger on falling edge = negative edge-triggered • Inputs must be stable just before the triggering edge input clock

Clock Disciplines • Level sensitive – State changes when clock is high (or low) • Edge triggered – State changes at clock edge positive edge-triggered negative edge-triggered

D Latch with Clock D S Q clk R Q S R Q Q 0 0 1 0 1 0 1 1 forbidden clk D Q Q 0 1 Q Q 1 0 0 1 1 0 15

D Latch with Clock D S Q clk R Q clk D Q Level Sensitive D Latch Clock high: set/reset (according to D) Clock low: keep state (ignore D) clk D Q Q 0 0 Q Q 0 1 Q Q 1 0 0 1 1 0 16

Edge-Triggered D Flip-Flop D D Q clk L Q X D c. L c Q Q Q Edge-Triggered • Data is captured Q when clock is high • Outputs change only on falling edges • clk D X Q 17

Registers D 0 D 1 D 2 Register • D flip-flops in parallel • shared clock • extra clocked inputs: write_enable, reset, … D 3 4 clk 4 -bit reg 4 18

Clock Methodology • Negative edge, synchronous clk tcombinational compute tsetup thold save compute – Signals must be stable near falling clock edge Positive edge synchronous • Asynchronous, multiple clocks, . . . • 19

Metastability and Asynchronous Inputs Q: What happens if select input changes near clock edge? A) Multiplexor selects input 0 B) Multiplexor selects input 1 C) Multiplexor chooses either input D) Unknown E) None above 1 -bit reg 0 1 select Clk A: Google “Buridan’s Principle” by Leslie Lamport 20

An Example: What will this circuit do? Reset Run WE R 32 -bit reg Decoder +1 Clk 21

Recap We can now build interesting devices with sensors • Using combinatorial logic We can also store data values • In state-holding elements • Coupled with clocks 22

Administrivia Make sure partner in same Lab Section this week Lab 2 is out Due in one week, next Monday, start early Work alone But, use your resources • Lab Section, Piazza. com, Office Hours, Homework Help Session, • Class notes, book, Sections, CSUGLab No Homework this week 23

Administrivia Check online syllabus/schedule • http: //www. cs. cornell. edu/Courses/CS 3410/2012 sp/schedule. html Slides and Reading for lectures Office Hours Homework and Programming Assignments Prelims (in evenings): • Tuesday, February 28 th • Thursday, March 29 th • Thursday, April 26 th Schedule is subject to change 24

Collaboration, Late, Re-grading Policies “Black Board” Collaboration Policy • Can discuss approach together on a “black board” • Leave and write up solution independently • Do not copy solutions Late Policy • Each person has a total of four “slip days” • Max of two slip days for any individual assignment • Slip days deducted first for any late assignment, cannot selectively apply slip days • For projects, slip days are deducted from all partners • 20% deducted per day late after slip days are exhausted Regrade policy • Submit written request to lead TA, and lead TA will pick a different grader • Submit another written request, lead TA will regrade directly • Submit yet another written request for professor to regrade. 25

Finite State Machines

detect Revisit Voting Machine Ballots 8 enc 3 7 LED decode 7 How do we create a vote counter machine 27

Revisit Voting Machine 32 reg reg WE WE WE . . . reg LED dec mux 32 32 +1 32 WE decoder (3 -to-8) V enc detect D 3 3 28

Finite State Machines An electronic machine which has • external inputs • externally visible outputs • internal state Output and next state depend on • inputs • current state 29

Abstract Model of FSM Machine is M = ( S, I, O, ) S: Finite set of states I: Finite set of inputs O: Finite set of outputs : State transition function Next state depends on present input and present state 30

Revisit Voting Machine 32 32 mux 32 reg reg WE WE WE . . . reg LED dec mux 3 +1 32 WE enc detect decoder (3 -to-8) 3 31

Automata Model Registers Finite State Machine • • Current State Input Comb. Logic Output Next State inputs from external world outputs to external world internal state combinational logic 32

FSM Example down/on input/output state B A start state Legend down/on up/off C Input: up or down Output: on or off States: A, B, C, or D D down/off 33

FSM Example down/on input/output state A start state Legend down/on up/off B up/off C down/off Input: = up or = down Output: = on or = off States: = A, = B, = C, or = D D down/off 34

FSM Example i 0 i 1 i 2…/o 0 o 1 o 2… 1/1 0/0 01 00 S 1 S 0 1/1 S 1 S 0 Legend 0/0 10 Input: 0=up or 1=down 1/0 Output: 1=on or 1=off States: 00=A, 01=B, 10=C, or 11=D 0/0 11 1/0 35

Mealy Machine Registers General Case: Mealy Machine Current State Input Comb. Logic Output Next State Outputs and next state depend on both current state and input 36

Moore Machine Registers Special Case: Moore Machine Current State Comb. Logic Output Input Comb. Logic Next State Outputs depend only on current state 37

Moore Machine Example down input state out up on off start out Legend B A up up C up D off Input: up or down Output: on or off States: A, B, C, or D down on down 38

Example: Digital Door Lock Inputs: • keycodes from keypad • clock Outputs: • “unlock” signal • display how many keys pressed so far 39

Door Lock: Inputs Assumptions: • signals are synchronized to clock • Password is B-A-B K A B K 0 1 1 A 0 1 0 B 0 0 1 Meaning Ø (no key) ‘A’ pressed ‘B’ pressed 40

Door Lock: Outputs Assumptions: • High pulse on U unlocks door D 3 D 2 D 1 D 0 4 LED 8 dec U 41

Door Lock: Simplified State Diagram Ø Ø G 1 ” 1” “A” “B” G 2 ” 2” else “B” else G 3 ” 3”, U any Idle ” 0” Ø else any B 1 ” 1” else B 2 ” 2” Ø else B 3 ” 3” Ø 42

Door Lock: Simplified State Diagram Ø Ø G 1 ” 1” else “B” Idle ” 0” Ø “A” G 2 ” 2” else “B” G 3 ” 3”, U any else B 1 ” 1” else B 2 ” 2” Ø Ø 43

Door Lock: Simplified State Diagram Ø Ø G 1 ” 1” else “B” Idle ” 0” Ø “A” G 2 ” 2” else “B” G 3 ” 3”, U Cur. any Output State else B 1 ” 1” else B 2 ” 2” Ø Ø 44

Door Lock: Simplified State Diagram Ø Ø G 1 ” 1” else “B” Idle ” 0” Ø “A” G 2 ” 2” else B 1 ” 1” else B 2 ” 2” Ø Ø “B” G 3 ” 3”, U Cur. any Output State Idle “ 0” G 1 “ 1” G 2 “ 2” G 3 “ 3”, U B 1 “ 1” B 2 “ 2” 45

Door Lock: Simplified State Diagram Ø Ø G 1 ” 1” else “B” Idle ” 0” Ø “A” Cur. State G 2 ” 2” else “B” Input Next State G 3 ” 3”, U any else B 1 ” 1” else B 2 ” 2” Ø Ø 46

Door Lock: Simplified State Diagram Ø Ø G 1 ” 1” else “B” Idle ” 0” Ø “A” else B 1 ” 1” else Ø Cur. State G 2 Idle “B” ” 2”Idle else. Idle G 1 G 1 G 2 G 2 B 2 G 3 ” 2” B 1 ØB 2 Input Next State Ø G 3 Idle ” 3”, U “B” G 1 “A” B 1 any Ø G 1 “A” G 2 “B” B 2 Ø B 2 “B” G 3 “A” Idle any Idle Ø B 1 K B 2 Ø B 2 K Idle 47

State Table Encoding SCur. SState S 0 D 3 2 1 0 Idle 0 0 G 1 0 0 G 2 1 0 0 0 G 3 1 1 0 1 B 1 0 0 0 1 B 2 0 1 0 State K D 3 D 2 D 1 AD 0 B 0 Idle 0 U 0 1 G 1 1 0 1 G 2 0 1 G 3 B 1 B 2 DOutput 2 D 1 D 0 0 “ 0” 0 0 0 “ 1” 0 1 0 “ 2” 1 0 0“ 3”, 1 U 1 0 “ 1” 0 1 0 “ 2” 1 0 U 0 0 0 1 0 0 4 Meaning S 2 S 1 8 S 0 dec 0 0 Ø 0(no key) 0 1 ‘A’ 0 pressed R 0 0 1 ‘B’ pressed P 0 1 1 Q 1 0 0 1 Cur. S 2 SState 1 S 0 0 Idle 0 0 0 G 1 0 1 0 G 2 1 0 0 G 3 1 1 1 B 1 0 0 1 B 2 0 1 K Input A B 0 Ø 0 0 1 “B” 0 1 1 “A” 1 0 0 Ø 0 0 1 “A” 1 0 1 “B” 0 1 0 Ø 0 0 1 “B” 0 1 1 “A” 1 0 x any x x 0 Ø 0 0 1 K x x Next S’ 2 S’State 1 S’ 0 0 Idle 0 0 0 G 1 0 1 1 B 1 0 0 0 G 1 0 G 2 1 0 1 B 2 0 1 0 B 2 1 0 0 G 3 1 1 0 Idle 0 0 1 B 1 0 0 1 B 2 0 1 0 Idle 0 0 48

3 bit Reg S 2 -0 D 3 -0 U 4 dec Door Lock: Implementation clk S 2 -0 A B S’ 2 -0 C Strategy: (1) Draw a state diagram (e. g. Moore Machine) (2) Write output and next-state tables (3) Encode states, inputs, and outputs as bits (4) Determine logic equations for next state and outputs 49

Summary We can now build interesting devices with sensors • Using combinational logic We can also store data values • • Stateful circuit elements (D Flip Flops, Registers, …) Clock to synchronize state changes But be wary of asynchronous (un-clocked) inputs State Machines or Ad-Hoc Circuits 50