LHO 12 Interfacing 1 A simple bus Wires
LHO 12 Interfacing 1
A simple bus • Wires: – Uni-directional or bi-directional – One line may represent multiple wires • Bus Processor – Set of wires with a single function • Address bus, data bus rd'/wr enable Memory addr[0 -11] data[0 -7] – Or, entire collection of wires • Address, data and control • Associated protocol: rules for communication bus structure 2
Timing Diagrams • Most common method for describing a communication protocol • Time proceeds to the right on x-axis • Control signal: low or high – May be active low (e. g. , go’, /go, or go_L) – Use terms assert (active) and deassert – Asserting go’ means go=0 • Data signal: not valid or valid • Protocol may have subprotocols – Called bus cycle, e. g. , read and write – Each may be several clock cycles • Read example – rd’/wr set low, address placed on addr for at least tsetup time before enable asserted, enable triggers memory to place data on data wires by time tread rd'/wr enable addr data tsetup tread protocol rd'/wr enable addr data tsetup twrite protocol 3
Microprocessor interfacing: I/O addressing • A microprocessor communicates with other devices using some of its pins – Port-based I/O (parallel I/O) • Processor has one or more N-bit ports • Processor’s software reads and writes a port just like a register • E. g. , P 0 = 0 x. FF; v = P 1. 2; -- P 0 and P 1 are 8 -bit ports – Bus-based I/O • Processor has address, data and control ports that form a single bus • Communication protocol is built into the processor • A single instruction carries out the read or write protocol on the bus 4
Types of bus-based I/O: memory-mapped I/O and standard I/O • Processor talks to both memory and peripherals using same bus – two ways to talk to peripherals – Memory-mapped I/O • Peripheral registers occupy addresses in same address space as memory • e. g. , Bus has 16 -bit address – lower 32 K addresses may correspond to memory – upper 32 k addresses may correspond to peripherals – Standard I/O (I/O-mapped I/O) • Additional pin (M/IO) on bus indicates whether a memory or peripheral access • e. g. , Bus has 16 -bit address – all 64 K addresses correspond to memory when M/IO set to 0 – all 64 K addresses correspond to peripherals when M/IO set to 1 5
Memory-mapped I/O vs. Standard I/O • Memory-mapped I/O – Requires no special instructions • Assembly instructions involving memory like MOV and ADD work with peripherals as well • Standard I/O requires special instructions (e. g. , IN, OUT) to move data between peripheral registers and memory • Standard I/O – No loss of memory addresses to peripherals – Simpler address decoding logic in peripherals possible • When number of peripherals much smaller than address space then high-order address bits can be ignored – smaller and/or faster comparators 6
Consider a simple processor. I call it the simple processing unit (SPU). 7
The memory read and I/O read timing for a simple processor is shown below. 8
The Memory write and I/O write timing for a simple processor is shown below. 9
I/O Ports 10
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Some Real processors No separate I/O address space. 12
No separate I/O address space. 13
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The 8051 Atmel AVR 17
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8051 19
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A basic memory protocol P 0 P 2 Q ALE /RD Adr. 7. . 0 Data P 0 Q D /CS Adr. 15… 8 ALE G A<0. . . 15> /OE /WE 74373 Adr. 7… 0 D<0. . . 7> 8 P 2 /WR /RD /PSEN 8051 CS 2 /CS 1 HM 6264 /CS D<0. . . 7> A<0. . . 14> /OE 27 C 256 • Interfacing an 8051 to external memory – Ports P 0 and P 2 support-based I/O when 8051 internal memory being used – Those ports serve as data/address buses when external memory is being used – 16 -bit address and 8 -bit data are time multiplexed; low 8 -bits of address must therefore be latched with aid of 22 ALE signal
8051 instructions for addressing external code and data memory. 23
D<0. . . 7> Q D P 0 A<0. . . 15> /CS ALE 74373 G /OE HM 6264 /WE CS 2 8051 P 2 /CS 1 8 /WR /CS /RD /PSE N D<0. . . 7> 27 C 256 Ex: XM(0) XM(1) MOV DPTR, #0 MOVX A, @DPTR INC DPTR MOV R 7, A MOVX A, @DPTR XCH A, R 7 MOVX @DPTR, A DEC DPTR XCH A, R 7 MOVX @DPTR, A A<0. . . 14> /OE Ex: XM(0) XM(1) CLR P 2 CLR R 0 MOV R 1, #1 MOVX A, @R 0 MOV R 7, A MOVX A, @R 1 MOVX @R 0, A MOV A, R 7 MOVX @R 1, A 24
Rn. C n_BUSY BYTE EQU P 1. 1 EQU P 1. 2 EQU P 1. 3 25
Rn. C EQU P 1. 1 n_BUSY EQU P 1. 2 BYTE EQU P 1. 3 CLR Rn. C SETB Rn. C JNB n_BUSY, $ MOV R 7, P 0 CPL BYTE MOV R 6, P 0 26
The 8255 27
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Change individual bits on Port C 32
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RESET_8255 EQU P 1. 0 CTL 1 EQU 11111011 B PRTA 1 EQU 11111000 B PRTB 1 EQU 11111001 B PRTC 1 EQU 11111010 B CTL 2 EQU 11110111 B PRTA 2 EQU 11110100 B PRTB 2 EQU 11110101 B PRTC 2 EQU 11110110 B ; ONE POSSIBLE ADDRESS FOR CONTROL PORT OF 8255 #1 ; ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1 ; ONE POSSIBLE ADDRESS FOR CONTROL PORT OF 8255 #2 ; ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2 CLR RESET_8255 ; REMOVE RESET FROM 8255 ; DO ADDITION C 2|C 1 <-- A 2|A 1 + B 2|B 1 MOV DPTR, #(CTL 1 AND CTL 2); POINT DPTR TO CONTROL REG OF 8255 #1 AND #2 MOV A, 10010010 B ; PRTA, PRTB IN, PRTC OUT MOVX @DPTR, A ; OUTPUT TO BOTH CONTROL REGS AT SAME TIME MOV DPTR, #PRTA 1 ; SELECT PORT A OF 8255 #1 MOVX A, @DPTR ; GET PRTA 1 MOV R 7, A ; SAVE IT MOV DPTR, #PRTB 1 ; SELECT PORT B OF 8255 #1 MOVX A, @DPTR ; READ PORT B OF 8255 #1 ADD A, R 7 ; ADD PRTA 1 TO PRTB 1 MOV DPTR, #PRTC 1 ; SELECT PORT C OF 8255 #1 MOVX @DPTR, A ; OUTPUT TO PRTC 1 END 34
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Figure 1. AT 90 S 8515 with expanded memory. What should we do with A 16? Answer: connect it to an unused port pin. Question: How could we map the entire 128 K bytes of memory to the top 32 Kbytes of the AVR address space. Answer: Connect AVR A 15 to /CE on U 4. Now the memory is selected only when the AVR addresses the top have of the memory address space where A 15 = 1. Connect A 15 and A 16 of U 4 to unused AVR port pins. By changing these port pin, any of the four 32 K byte pages of U 4 memory can be switched in and out of the AVR address space. 38
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