IT 252 Computer Organization and Architecture Introduction ChiaChi

IT 252 Computer Organization and Architecture Introduction Chia-Chi Teng

What is computer architecture about? • • Computer architecture is the study of building computer systems. IT 252 is roughly split into four parts. – First, we will discusses instruction set architectures—the bridge between hardware and software. – Second, we introduce more advanced processor implementations. The focus is on pipelining, which is one of the most important ways to improve performance. – Next, we talk about memory systems, I/O, and how to connect it all together. – We will also introduce you to Assembly and C programming through out the course.

Why should you care? • • It is interesting. – You will learn how a processor actually works! It will help you be a better programmer. – Understanding how your program is translated to assembly code lets you reason about correctness and performance. – Demystify the seemingly arbitrary (e. g. , bus errors, segmentation faults) Many cool jobs require an understanding of computer architecture. – The cutting edge is often pushing computers to their limits. – Supercomputing, games, portable devices, etc. Computer architecture illustrates many fundamental ideas in all computing discipline. – Abstraction, caching, and indirection …

Personnel § Lecturer — Prof. Chia-Chi Teng • ccteng@byu. edu — Office hours • MW 10 -12 • Or by appointment § TA — Michael Zanandrea (Lab) • thefastone 11@hotmail. com — Francis Mensah (Lab & Homework) • nobcis@yahoo. com — TA Office hours • TBD § Course webpage: http: //it 252. groups. et. byu. net/12 wi/IT 252. php

Administrivia • The textbooks provides the most comprehensive coverage – "Computer Systems: A Programmer's Perspective" 2 nd Edition, by Randal E. Bryant & David R. O'Hallaron – The C Programming Language, Kernighan & Ritchie, 2 nd ed. • Read the text prior to class • class will supplement rather than regurgitate the text • IT curriculum changes in Fall 2010 • IT 251 (4) -> IT 252 (3) • IT 104 B (2) -> CS/ECEn 124 (3) • IT 104 A (2) -> part of IT 327 (4) • Did you take 104 or 124?

Grading • Professionalism: Attendance, Attitude, Participation, 5% final grade • Homework – Usually due on every Friday and Monday, check course website often for detail and update, 25% final grade • Quizzes - about 6 – 8, take home, 10 pts each, 15% final grade • Lab reports – Due date to be specified by TA, 25% final grade • Exams - final and at least one mid-term; usually open-book, take home, untimed 30%

Homework • Homework exercises provide added impetus to keep up with the reading. • Textbook problems • Assignments are listed on course web page by weeks, usually due on Monday of the following week. • • Turn in: on blackboard AND in paper. Homework locker. We really want to encourage discussion, both in class and in lab. But zero tolerance for cheating, don’t go there. Don’t look for solutions online. • HW 1 due two weeks from today on 9/12, due to Labor day. Start early.

Labs § No lab this week. Lab 1 next week. § Room 335 — Hardware Description Language (VHDL), CPU design § Room 365 — Memory system, I/O … § Lab report: TA will give you detail

To-Do list • Read chapter 1 before Thursday • please read the entire course web thoroughly, today • Course web is work in progress, please check back often IT 252 blackboard check your email daily keep up with the reading: this week … homework due – Check website (again, turn in on Blackboard & on paper) • lab report due – TA discretion via blackboard • •

What is Computer Architecture? It’s the study of the ______ of computers § Structure: static arrangement of the parts § Organization: dynamic interaction of the parts and their control § Implementation: design of specific building blocks § Performance: behavioral study of the system or of some of its components 12/1/2020 10

Another definition: Instruction Set Architecture (ISA) • Architecture is an interface between layers • ISA is the interface between hardware and software • ISA is what is visible to the programmer (and ISA might be different for OS and applications) • ISA consists of: – instructions (operations and how they are encoded) – information units (size, how they are addressed etc. ) – registers (or more generally processor state) – input-output control 12/1/2020 11

Computer structure: Von Neumann model 1945 Data path CPU Memory hierarchy control Registers + Control ALU I/O PC state Memory bus 12/1/2020 I/O bus 12

Computer Organization • Organization and architecture often used as synonyms • Organization (in this course) refers to: – what are the basic blocks of a computer system, more specifically • basic blocks of the CPU • basic blocks of the memory hierarchy – how are the basic blocks designed, controlled, connected? • Organization used to be transparent to the ISA. • Today more and more of the ISA is “exposed” to the user/compiler. 12/1/2020 13

Moore’s Law • In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 24 months (i. e. , grow exponentially with time). • Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s. – 2300 transistors, 1 MHz clock (Intel 4004) - 1971 – 16 Million transistors (Ultra Sparc III) – 42 Million transistors, 2 GHz clock (Intel Xeon) – 2001 – 55 Million transistors, 3 GHz, 130 nm technology, 250 mm 2 die (Intel Pentium 4) - 2004 – 140 Million transistors (HP PA-8500) – Today: 2. 6 Billion transistors (10 -core Xeon) – http: //en. wikipedia. org/wiki/Transistor_count

Illustration of Moore’s Law

Power Dissipation 12/1/2020 16

Evolution of Intel Microprocessor Speeds How about today? 12/1/2020 17

POLL § Which type of CPU has the largest worldwide market share? — Intel — AMD — ARM — MIPS § http: //www. polleverywhere. com/multipl e_choice_polls/LTE 2 OTY 2 Mj. I

Millions of Computers Where is the Market?

Millions of Processor ISA Type Sales What’s in your cell phone?

Processor Performance Increase DEC Alpha 21264 A/667 DEC Alpha 21264/600 DEC Alpha 4/266 DEC AXP/500 SUN-4/260 IBM RS 6000 MIPS M 2000 MIPS M/120 DEC Alpha 5/500 DEC Alpha 5/300 IBM POWER 100 HP 9000/750 Intel Pentium 4/3000 Intel Xeon/2000

DRAM Capacity Growth 64 M 16 M 4 M 1 M 256 K 64 K 16 K 512 M 256 M 128 M

Impacts of Advancing Technology • Processor – logic capacity: – performance: increases about 30% per year 2 x every 1. 5 years Clock. Cycle = 1/Clock. Rate 500 MHz Clock. Rate = 2 nsec Clock. Cycle 1 GHz Clock. Rate = 1 nsec Clock. Cycle 4 GHz Clock. Rate = 250 psec Clock. Cycle • • Memory – DRAM capacity: – memory speed: – cost per bit: Disk – capacity: 4 x every 3 years, now 2 x every 2 years 1. 5 x every 10 years decreases about 25% per year increases about 60% per year

Example Machine Organization • Typical workstation design target – 25% of cost on processor – 25% of cost on memory (minimum memory size) – Rest on I/O devices, power supplies, box Computer CPU Memory Devices Control Input Datapath Output

PC Motherboard Closeup

Inside the Pentium 4 Processor Chip

Some Computer families • • • Computers that have the same (or very similar) ISA – Compatibility of software between various implementations IBM – 704, 709, 70 xx etc. . From 1955 till 1965 – 360, 370, 43 xx, 33 xx From 1965 to the present – Power PC DEC – PDP-11, VAX From 1970 till 1985 – Alpha (now Compaq, now HP) in 1990’s 12/1/2020 27

More computer families • • • Intel – Early micros 40 xx in early 70’s – x 86 (086, …, 486, Pentium Pro, Pentium 3, Pentium 4) from 1980 on – IA-64 (Itanium) in 2001 SUN – Sparc, Ultra Sparc 1985 0 n MIPS-SGI – Mips 2000, 3000, 4400, 10000 from 1985 on – CISC vs RISC – Complex Instruction Set vs Reduced Instruction Set – What is an instruction? 12/1/2020 28

C program: foo. c Where Are We Now? Compiler Assembly program: foo. s CS 142 & 124 Assembler Object (mach lang module): foo. o Linker lib. o Executable (mach lang pgm): a. out IT 344 Loader Memory

Registers • Registers are the “bricks” of the CPU • Registers are an essential part of the ISA – Visible to the hardware and to the programmer • Registers are – Used for high speed storage for operands. For example, if variables i, j are in registers ax, cx respectively add ax, cx #i=i+j – Easy to name (most computers have limited number of registers visible to the programmer) – Used for addressing memory 12/1/2020 30

Registers (ct’d) • Not all registers are “equal” – Some are special-purpose (e. g. program counter, stack pointer) – Some are used for integer and some for floating-point – Some have restricted use by convention 12/1/2020 31

Memory system § Memory is a hierarchy of devices with faster and more expensive ones closer to CPU — Registers — Caches (hierarchy: on-chip, off-chip) — Main memory (DRAM) — Secondary memory (disks) 12/1/2020 CSE 378 Gen. Intro 32

Information units § Basic unit is the bit (has value 0 or 1) § Bits are grouped together in units and operated on together: — Byte = 8 bits — Word = 2 or 4 bytes — Double word = 2 words — Etc. § Integer: usually 4 bytes 12/1/2020 CSE 378 Gen. Intro 33

Memory addressing • Memory is an array of information units – Each unit has the same size – Each unit has its own address – Address of an unit and contents of the unit at that address are different 0 1 2 -123 17 0 contents address 12/1/2020 34

Addressing • • In most of today’s computers, the basic unit that can be addressed is a byte. (how many bit is a byte? ) – MIPS (and pretty much all CPU today) is byte addressable The address space is the set of all memory units that a program can reference – The address space is usually tied to the length of the registers – Intel 384/486/Pentium has 32 -bit registers. Hence its basic address space is 4 G bytes – MIPS has 32 -bit registers. – Older micros (minis) had 16 -bit registers, hence 64 KB address space (too small) – Some current (Intel Core. X, Alpha, Itanium, Sparc, Altheon) machines have 64 -bit registers, hence an enormous address space 12/1/2020 35

Addressing words § § Although machines are byte-addressable, 4 byte integers are the most commonly used units Every 32 -bit word starts at an address divisible by 4 int at address 0 int at address 4 int at address 8 12/1/2020 36

Big-endian vs. little-endian § Byte order within an int: Memory address int #0 § § 3 2 1 0 1 2 0 3 Little-endian (we’ll use this) 0 1 2 3 byte int #0 Big-endian RS-232 Ethernet Frame 12/1/2020 37

The CPU - Instruction Execution Cycle § § The CPU executes a program by repeatedly following this cycle 1. Fetch the next instruction, say instruction i 2. Execute instruction i 3. Compute address of the next instruction, say j 4. Go back to step 1 Of course we’ll optimize this but it’s the basic concept 12/1/2020 38

What’s in an instruction? • • • An instruction tells the CPU – the operation to be performed via the OPCODE – where to find the operands (source and destination) For a given instruction, the ISA specifies – what the OPCODE means (semantics) – how many operands are required and their types, sizes etc. (syntax) Operand is either – register (integer, floating-point, PC) – a memory address – a constant 12/1/2020 39