Computer Organization EEC213 Computer Organization Electrical and Computer

Computer Organization EEC-213 Computer Organization Electrical and Computer Engineering 10/28/2020 445_01 1

Grading w Homework w Midterm Exam w Oral Exam w Final Exam 10/28/2020 10% 20% 60% 445_01 2

Honor Code w You are encouraged to discuss homework problems with other students and/or obtain the assistance of the instructor. n Nevertheless, homework submissions should be the work of you and your partner. w Exams are closed book, closed notes, no use of calculators, and the normal honor code applies to all exams. 10/28/2020 445_01 3

Textbooks w Computer Organization, 5 th ed. n n n Carl Hamacher, et al. , ISBN 0 -07 -232086 -9 2002 10/28/2020 445_01 4

Questions? 10/28/2020 445_01 5

Basic structure of Computers 10/28/2020 445_02 6

Computer Functional Units Arithmetic & Logic Input Memory Output Control I/O Processor 10/28/2020 445_01 7

Course Organization w w Computer Structure (Ch 1) Instruction Sets & Addressing Modes (Ch 2) Example Computer: Motorola 68000 (Ch 3) Control Unit Design (Ch 7) w w Computer Arithmetic (Ch 6) Memory (Ch 5) Input/Output (Ch 4) Pipelining (Ch 8) 10/28/2020 445_01 8

Computer Information (Binary) w (Machine) Instructions n (Machine Language) Programs w Data n n n 2's complement BCD ASCII 10/28/2020 445_01 9

I/O w Input n n n w Output Keyboard Mouse Microphone Camera Scanner n n n Display Printer Speakers w Serial Communications n n 10/28/2020 Network Modem 445_01 10

Memory w Primary n n w Secondary Random Access Memory (RAM) Read Only Memory (ROM) n l l n n n Word Address Read/Write 10/28/2020 Disks Tape Optical Disks w Hierarchy w Organization n Magnetic n n n 445_01 Cache Main Virtual 11

ALU w Arithmetic n n n w Logic Addition Subtraction Multiplication Division Comparison n n AND OR NOT XOR w Registers n n 10/28/2020 Store Shift 445_01 12

Control Unit w Coordinates/Directs other Units w Computer Operation n Input l n Program/Data stored in Memory Processing Information fetched into Registers l Processed by ALU l n Output 10/28/2020 445_01 13

Computer Instructions w Assembly Language w Register Transfer Notation n MOVE NUM 1, R 1 n R 1 [NUM 1] n MOVE #1, R 2 n R 2 1 n ADD #1, R 1 n R 1 1 + [R 1] n ADD R 1, R 2 n R 2 [R 1] + [R 2] 10/28/2020 445_02 14

Processor and Memory MEM MAR MDR PC R 0 R 1 IR . . . Rn-1 Control ALU Processor MAR - Memory Address Register PC - Program Counter MDR - Memory Data Register IR - Instruction Register 10/28/2020 445_02 15

Example Instruction MOVE NUM 1, R 1 w Fetch n n w Execute MAR [PC] PC [PC] + 1 MDR [MEM(MAR)] IR [MDR] 10/28/2020 445_02 n n n MAR NUM 1 MDR [MEM(MAR)] R 1 [MDR] 16

Another Example ADD #1, R 1 w Fetch n n w Execute MAR [PC] PC [PC] + 1 MDR [MEM(MAR)] IR [MDR] 10/28/2020 445_02 n R 1 1 + R 1 17

Single-Bus Structure • The computer parts must be connected in some way • A group of lines that serves as a connecting path for several devices is called bus • Only one transfer at a time can occurs between 2 units • Devices includes a buffer register to hold information during transfer Input Output 10/28/2020 Memory 445_02 Processor 18

Single-Bus Architecture (HW 1) BUS A MAR MEM MDR Y A ALU R B Z 10/28/2020 445_02 19

System Software w Compiler n High-level Language Machine Language w Assembler n Assembly Language Machine Language w Text Editor n Keyboard Input File w Operating System n n Control Sharing & Interaction Assign & Manage Resources l l n Memory Disk Space Handle I/O 10/28/2020 445_02 20

Memory Performance w Programs and data are stored in memory w Instruction are fetched one by one over the bus to the processor, and a copy is placed in the cache. w When a data is executed by an instruction a copy is placed in the cache w Later if the same instruction or data item is needed a second time , it’s red directly from the cache. w Execution of instruction and data from the cache is faster than the main memory Main Memory 10/28/2020 Cache Memory 445_02 Processor 21

Processor Clock CLK w Period (P) w R = 1/P w Rate (R) w 1 GHz = 1/1 ns 10/28/2020 445_02 22

Performance Equation w w Processor Execution Time (T) Number of Machine Language Instructions (N) Average Steps per Machine Instruction (S) Clock Rate (R) w Performance of a processor of 2. 4 GHz & a processor of 2. 8 GHz of another type. 10/28/2020 445_02 23

Pipelining I 1 F 1 I 2 E 1 F 2 I 3 E 2 F 3 E 3 Sequential Execution I 1 F 1 I 2 E 1 F 2 I 3 E 2 F 3 E 3 Pipelined Execution 10/28/2020 445_02 24

Parallel Processing w Parallel Execution n Superscalar (execution of several instructions in every clock cycle) w Multiprocessors n Shared-Memory w Multicomputers n Message-Passing 10/28/2020 445_02 25

CISC vs RISC w Complex Instruction Set Computers (CISC) n n Smaller N Larger S w Reduced Instruction Set Computers (RISC) n n n Larger N Smaller S Easier to Pipeline 10/28/2020 445_02 26

History w First Generation (miliseconds) n n von Neumann (stored program) Vacuum Tubes Magnetic Core Memory Teletypes/Magnetic Tapes w Second Generation (microseconds) n n Transistor High-level Languages (C++, Pascal, Fortran) l n Compilers (translate HHL to M/C instruction) I/O Processors 10/28/2020 445_01 27

History w Third Generation n n Integrated Circuits Microprogramming Parallelism/Pipelining Operating Systems (sharing) Cache/VM w Fourth Generation (nanoseconds) n n n VLSI (Single Chip Microprocessor) Personal Computers Networks 10/28/2020 445_01 28

Problem 1 -3 n n n n Load A, R 0 Load B, R 1 Add R 0, R 1 Store R 1, C (b) Yes; Move B, C Add A, C 10/28/2020 445_02 29

Review w Binary w Hex w 2's-complement w Overflow 10/28/2020 445_02 30