Computer Organization and Architecture Introduction Architecture Organization 1

Computer Organization and Architecture Introduction

Architecture & Organization 1 z Architecture is those attributes visible to the programmer y. Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques. ye. g. Is there a multiply instruction? z Organization is how features are implemented, typically hidden from the programmer y. Control signals, interfaces, memory technology. ye. g. Is there a hardware multiply unit or is it done by repeated addition?

Architecture & Organization 2 z All Intel x 86 family share the same basic architecture z The IBM System/370 family share the same basic architecture z This gives code compatibility y At least backwards y But… increases complexity of each new generation. May be more efficient to start over with a new technology, e. g. RISC vs. CISC z Organization differs between different versions

Levels of Machines Computers are complex; easier to understand if broken up into hierarchical components.

Structure & Function z At each level the designer should consider y. Structure : the way in which components relate to each other y. Function : the operation of individual components as part of the structure z Let’s look at the computer hardware top-down starting with function. y. Later we’ll look at software

Function z All computer functions are: y. Data processing y. Data storage y. Data movement y. Control

Functional view z Functional view of a computer Data Storage Facility Data Movement Apparatus Control Mechanism Data Processing Facility

Operations (1) z Data movement ye. g. keyboard to screen Data Movement Apparatus Data Storage Facility Control Mechanism Data Processing Facility

Operations (2) z Storage ye. g. Internet download to disk Data Movement Apparatus Data Storage Facility Control Mechanism Data Processing Facility

Operation (3) z Processing from/to storage ye. g. updating bank statement Data Movement Apparatus Data Storage Facility Control Mechanism Data Processing Facility

Operation (4) z Processing from storage to I/O ye. g. printing a bank statement Data Movement Apparatus Data Storage Facility Control Mechanism Data Processing Facility

Structure z Major Components of a Computer y. Central Processing Unit (CPU) – Controls the operation of the computer and performs data processing y. Main Memory – Stores data y. Input Output (I/O) – Moves data between the computer and the external environment y. System Interconnect – Some mechanism that provides for communications between the system components, typically a bus (set of wires)

Structure - Top Level Peripherals Computer Central Processing Unit Computer Systems Interconnection Input Output Communication lines Main Memory

Generic System Bus = Data, Address, and Control Bus (set of wires, e. g. 32 wires each) Typically multiple I/O buses, power bus, etc.

Structure - CPU z Major components of the CPU y. Control Unit (CU) – Controls the operation of the CPU y. Arithmetic and Logic Unit (ALU) – Performs data processing functions, e. g. arithmetic operations y. Registers – Fast storage internal to the CPU, but contents can be copied to/from main memory y. CPU Interconnect – Some mechanism that provides for communication among the control unit, ALU, and registers

Structure - The CPU Computer Arithmetic and Login Unit Registers I/O System Bus Memory CPU Internal CPU Interconnection Control Unit

Structure – Inside the CPU z The implementation of registers and the ALU we will leave primarily to EE 241 z We will say a bit about the architecture of the control unit, there are many possible approaches. y. A common approach is the microprogrammed control unit, where the control unit is in essence itself a miniature computer, where a CPU instruction is implemented via one or more “micro instructions” x. Sequencing Logic – Controlling the order of events x. Microprogram Control Unit – Internal controls x. Microprogram Registers, Memory

Structure – A Microprogrammed Control Unit CPU Sequencing Login ALU Internal Bus Registers Control Unit Registers and Decoders Control Memory

Computer Evolution and Performance Better, Faster, Cheaper?

History: ENIAC background z Electronic Numerical Integrator And Computer z Eckert and Mauchly z University of Pennsylvania z Trajectory tables for weapons, BRL z Started 1943 z Finished 1946 y. Too late for war effort z Used until 1955

ENIAC - details z Decimal (not binary) z 20 accumulators of 10 digits (ring of 10 tubes) z Programmed manually by switches z 18, 000 vacuum tubes z 30 tons z 15, 000 square feet z 140 k. W power consumption (about $10/hr today) z 5, 000 additions per second

Vacuum Tubes Grid regulates flow from of electrons from the cathode

von Neumann/Turing z ENIAC : Very tedious to manually wire programs z von Neumann architecture: y. Stored Program concept y. Main memory storing programs and data y. ALU operating on binary data y. Control unit interpreting instructions from memory and executing y. Input and output equipment operated by control unit y. Princeton Institute for Advanced Studies x. IAS y. Completed 1952

Structure of von Neumann machine Arithmetic and Logic Unit Input Output Equipment Main Memory Program Control Unit

IAS - details z 1000 x 40 bit words y Binary number y 2 x 20 bit instructions Sign bit 01 39 Number Word z Set of registers (storage in CPU) y Memory Buffer Register y Memory Address Register y Instruction Buffer Register y Program Counter y Accumulator y Multiplier Quotient Left Right Op. Code Address 0 8 20 Instruction Word 28 39

Structure of IAS - detail Central Processing Unit Arithmetic and Logic Unit Accumulator MQ Arithmetic & Logic Circuits MBR Input Output Equipment Instructions Main & Data Memory PC IBR MAR IR Control Circuits Program Control Unit Address

IAS Instruction Cycle z The IAS repetitively performs the instruction cycle: y Fetch x. Opcode of the next instruction is loaded into the IR x. Address portion is loaded into the MAR x. Instruction either taken from the IBR or obtained from memory by loading the PC into the MAR, memory to the MBR, then the MBR to the IBR and the IR • To simplify electronics, only one data path from MBR to IR y Execute x. Circuitry interprets the opcode and executes the instruction x. Moving data, performing an operation in the ALU, etc. z IAS had 21 instructions y Data transfer, Unconditional branch, arithmetic, address modification

Commercial Computers z 1947 - Eckert-Mauchly Computer Corporation z UNIVAC I (Universal Automatic Computer) z US Bureau of Census 1950 calculations z Became part of Sperry-Rand Corporation z Late 1950 s - UNIVAC II y. Faster y. More memory y. Upward compatible with older machines

IBM z Punched-card processing equipment z 1953 - the 701 y. IBM’s first stored program computer y. Scientific calculations z 1955 - the 702 y. Business applications z Lead to 700/7000 series

Transistors z Replaced vacuum tubes z Smaller z Cheaper z Less heat dissipation z Solid State device z Made from Silicon (Sand) z Invented 1947 at Bell Labs z Shockley, Brittain, Bardeen

Transistor Based Computers z Second generation of machines z NCR & RCA produced small transistor machines z IBM 7000 z DEC - 1957 y. Produced PDP-1

IBM 7094 z Last member of the 7000 series y 50 times faster than the 701 x 1. 4 u. S vs. 30 u. S cycle y 32 K memory vs. 2 K y. Main memory: Core memory vs. Tubes y. CPU memory: transistors vs. Tubes y 185 vs. 24 opcodes y. Instruction fetch overlap, reduced another trip to memory (exception are branches) y. Data channels, independent I/O module for devices

3 rd Generation: Integrated Circuits z Self-contained transistor is a discrete component y. Big, manufactured separately, expensive, hot when you have thousands of them z Integrated Circuits y. Transistors “etched” into a substrate, bundled together instead of discrete components y. Allowed thousands of transistors to be packaged together efficiently

Microelectronics z Literally - “small electronics” z A computer is made up of gates, memory cells and interconnections z These can be manufactured on a semiconductor, e. g. silicon wafer y. Thin wafer divided into chips y. Each chip consists of many gates/memory cells y. Chip packaged together with pins, assembled on a printed circuit board

Generations of Computer z Vacuum tube - 1946 -1957 z Transistor - 1958 -1964 z Small scale integration - 1965 on y Up to 100 devices on a chip z Medium scale integration - to 1971 y 100 -3, 000 devices on a chip z Large scale integration - 1971 -1977 y 3, 000 - 100, 000 devices on a chip z Very large scale integration - 1978 to date y 100, 000 - 100, 000 devices on a chip y Pentium IV has about 40 million transistors z Ultra large scale integration y Over 100, 000 devices on a chip (vague term)

Moore’s Law z Increased density of components on chip z Gordon Moore : co-founder of Intel z Number of transistors on a chip will double every year z Since 1970’s development has slowed a little y Number of transistors doubles every 18 months z Cost of a chip has remained almost unchanged z Higher packing density means shorter electrical paths, giving higher performance z Smaller size gives increased flexibility z Reduced power and cooling requirements z Fewer interconnections increases reliability z Intel 8/13/02: Announced 0. 09 micron process y. Human hair ~70 microns

Growth in CPU Transistor Count

IBM 360 series z 1964 z Replaced (& not compatible with) 7000 series y Reason: Needed to break out of constraints of the 7000 architecture z First planned “family” of computers y Similar or identical instruction sets y Similar or identical O/S y Increasing speed y Increasing number of I/O ports (i. e. more terminals) y Increased memory size y Increased cost (not always the case today!) z Multiplexed switch structure

DEC PDP-8 z 1964 z First minicomputer (after miniskirt!) z Did not need air conditioned room z Small enough to sit on a lab bench z $16, 000 y$100 k+ for IBM 360 z Embedded applications & OEM z BUS STRUCTURE

DEC - PDP-8 Bus Structure Console Controller CPU Main Memory I/O Module OMNIBUS 96 separate signal paths to carry control, address, data signals Highly flexible, allowed modules to be plugged in for different configurations

Other Innovations Semiconductor Memory z 1970 z Fairchild z Size of a single core yi. e. 1 bit of magnetic core storage y. Held 256 bits z Non-destructive read z Much faster than core z Capacity approximately doubles each year

Intel z 1971 - 4004 y First microprocessor y All CPU components on a single chip y 4 bit z Followed in 1972 by 8008 y 8 bit y Both designed for specific applications z 1974 - 8080 y Intel’s first general purpose microprocessor z Evolution: 8086, 8088, 80286, 80386, 80486, Pentium Pro, Pentium III, Pentium IV, Itanium

Speeding it up z Smaller manufacturing process (0. 09 micron) z Pipelining z On board cache z On board L 1 & L 2 cache z Branch prediction z Data flow analysis z Speculative execution z Parallel execution

Performance Mismatch z Processor speed increased z Memory capacity increased z Memory speed lags behind processor speed z Common memory chip technology y. DRAM = Dynamic Random Access Memory

DRAM and Processor Characteristics

Trends in DRAM use

Solutions z Increase number of bits retrieved at one time y Make DRAM “wider” rather than “deeper” z Change DRAM interface y Cache z Reduce frequency of memory access y More complex cache and cache on chip z Increase interconnection bandwidth y High speed buses y Hierarchy of buses z Similar problems with I/O devices, e. g. graphics, network z Need balance in computer design