EECS 252 Graduate Computer Architecture Lecture 2 0

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EECS 252 Graduate Computer Architecture Lecture 2 0 Review of Instruction Sets, Pipelines, and

EECS 252 Graduate Computer Architecture Lecture 2 0 Review of Instruction Sets, Pipelines, and Caches January 25 th, 2010 John Kubiatowicz Electrical Engineering and Computer Sciences University of California, Berkeley http: //www. eecs. berkeley. edu/~kubitron/cs 252

Review: Moore’s Law • “Cramming More Components onto Integrated Circuits” – Gordon Moore, Electronics,

Review: Moore’s Law • “Cramming More Components onto Integrated Circuits” – Gordon Moore, Electronics, 1965 • 1/25/2010 # on transistors on cost effective integrated circuit double every 18 months CS 252 S 10, Lecture 02 2

Review: Joy’s Law in Many. Core world From Hennessy and Patterson, Computer Architecture: A

Review: Joy’s Law in Many. Core world From Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 4 th edition, October, 2006 • VAX : 25%/year 1978 to 1986 • RISC + x 86: 52%/year 1986 to 2002 • RISC + x 86: ? ? %/year 2002 to present 1/25/2010 CS 252 S 10, Lecture 02 3

Time (processor cycle) Review: Categories of Thread Execution Superscalar Simultaneous Fine Grained. Coarse Grained.

Time (processor cycle) Review: Categories of Thread Execution Superscalar Simultaneous Fine Grained. Coarse Grained. Multiprocessing. Multithreading Thread 1 Thread 2 1/25/2010 Thread 3 Thread 4 CS 252 S 10, Lecture 02 Thread 5 Idle slot 4

log (people per computer) “Bell’s Law” – new class per decade Number Crunching Data

log (people per computer) “Bell’s Law” – new class per decade Number Crunching Data Storage productivity interactive • Enabled by technological opportunities streaming information to/from physical world year • Smaller, more numerous and more intimately connected • Brings in a new kind of application • Used in many ways not previously imagined 1/25/2010 CS 252 S 10, Lecture 02 5

Today: Quick review of everything you should have learned 0 ( A countably infinite

Today: Quick review of everything you should have learned 0 ( A countably infinite set of computer architecture concepts ) 1/25/2010 CS 252 S 10, Lecture 02 6

Metrics used to Compare Designs • Cost – Die cost and system cost •

Metrics used to Compare Designs • Cost – Die cost and system cost • Execution Time – average and worst case – Latency vs. Throughput • Energy and Power – Also peak power and peak switching current • Reliability – Resiliency to electrical noise, part failure – Robustness to bad software, operator error • Maintainability – System administration costs • Compatibility – Software costs dominate 1/25/2010 CS 252 S 10, Lecture 02 7

What is Performance? • Latency (or response time or execution time) – time to

What is Performance? • Latency (or response time or execution time) – time to complete one task • Bandwidth (or throughput) – tasks completed per unit time 1/25/2010 CS 252 S 10, Lecture 02 8

Definition: Performance • Performance is in units of things per sec – bigger is

Definition: Performance • Performance is in units of things per sec – bigger is better • If we are primarily concerned with response time performance(x) = 1 execution_time(x) " X is n times faster than Y" means Performance(X) n = Execution_time(Y) = Performance(Y) 1/25/2010 CS 252 S 10, Lecture 02 Execution_time(X) 9

Performance: What to measure • Usually rely on benchmarks vs. real workloads • To

Performance: What to measure • Usually rely on benchmarks vs. real workloads • To increase predictability, collections of benchmark applications benchmark suites are popular • SPECCPU: popular desktop benchmark suite – – CPU only, split between integer and floating point programs SPECint 2000 has 12 integer, SPECfp 2000 has 14 integer pgms SPECCPU 2006 to be announced Spring 2006 SPECSFS (NFS file server) and SPECWeb (Web. Server) added as server benchmarks • Transaction Processing Council measures server performance and cost performance for databases – – 1/25/2010 TPC C Complex query for Online Transaction Processing TPC H models ad hoc decision support TPC W a transactional web benchmark TPC App application server and web services benchmark CS 252 S 10, Lecture 02 10

Summarizing Performance System Rate (Task 1) Rate (Task 2) A 10 20 B 20

Summarizing Performance System Rate (Task 1) Rate (Task 2) A 10 20 B 20 10 Which system is faster? 1/25/2010 CS 252 S 10, Lecture 02 11

… depends who’s selling System Rate (Task 1) Rate (Task 2) Average A 10

… depends who’s selling System Rate (Task 1) Rate (Task 2) Average A 10 20 15 B 20 10 15 Average throughput System Rate (Task 1) Rate (Task 2) Average A 0. 50 2. 00 1. 25 B 1. 00 Throughput relative to B System Rate (Task 1) Rate (Task 2) Average A 1. 00 B 2. 00 0. 50 1. 25 Throughput relative to A 1/25/2010 CS 252 S 10, Lecture 02 12

Summarizing Performance over Set of Benchmark Programs Arithmetic mean of execution times ti (in

Summarizing Performance over Set of Benchmark Programs Arithmetic mean of execution times ti (in seconds) 1/n i ti Harmonic mean of execution rates ri (MIPS/MFLOPS) n/ [ i (1/ri)] • Both equivalent to workload where each program is run the same number of times • Can add weighting factors to model other workload distributions 1/25/2010 CS 252 S 10, Lecture 02 13

Normalized Execution Time and Geometric Mean • Measure speedup up relative to reference machine

Normalized Execution Time and Geometric Mean • Measure speedup up relative to reference machine ratio = t. Ref/t. A • Average time ratios using geometric mean n ( I ratioi ) • Insensitive to machine chosen as reference • Insensitive to run time of individual benchmarks • Used by SPEC 89, SPEC 92, SPEC 95, …, SPEC 2006 …. . But beware that choice of reference machine can suggest what is “normal” performance profile: 1/25/2010 CS 252 S 10, Lecture 02 14

Vector/Superscalar Speedup • 100 MHz Cray J 90 vector machine versus 300 MHz Alpha

Vector/Superscalar Speedup • 100 MHz Cray J 90 vector machine versus 300 MHz Alpha 21164 • [LANL Computational Physics Codes, Wasserman, ICS’ 96] • Vector machine peaks on a few codes? ? 1/25/2010 CS 252 S 10, Lecture 02 15

Superscalar/Vector Speedup • 100 MHz Cray J 90 vector machine versus 300 MHz Alpha

Superscalar/Vector Speedup • 100 MHz Cray J 90 vector machine versus 300 MHz Alpha 21164 • [LANL Computational Physics Codes, Wasserman, ICS’ 96] • Scalar machine peaks on one code? ? ? 1/25/2010 CS 252 S 10, Lecture 02 16

How to Mislead with Performance Reports • • • Select pieces of workload that

How to Mislead with Performance Reports • • • Select pieces of workload that work well on your design, ignore others Use unrealistic data set sizes for application (too big or too small) Report throughput numbers for a latency benchmark Report latency numbers for a throughput benchmark Report performance on a kernel and claim it represents an entire application • Use 16 bit fixed point arithmetic (because it’s fastest on your system) even though application requires 64 bit floating point arithmetic • Use a less efficient algorithm on the competing machine • Report speedup for an inefficient algorithm (bubblesort) • Compare hand optimized assembly code with unoptimized C code • Compare your design using next year’s technology against competitor’s year old design (1% performance improvement per week) • Ignore the relative cost of the systems being compared • Report averages and not individual results • Report speedup over unspecified base system, not absolute times • Report efficiency not absolute times • Report MFLOPS not absolute times (use inefficient algorithm) [ David Bailey “Twelve ways to fool the masses when giving performance results for parallel supercomputers” ] 1/25/2010 CS 252 S 10, Lecture 02 17

Amdahl’s Law Best you could ever hope to do: 1/25/2010 CS 252 S 10,

Amdahl’s Law Best you could ever hope to do: 1/25/2010 CS 252 S 10, Lecture 02 18

Amdahl’s Law example • New CPU 10 X faster • I/O bound server, so

Amdahl’s Law example • New CPU 10 X faster • I/O bound server, so 60% time waiting for I/O • Apparently, its human nature to be attracted by 10 X faster, vs. keeping in perspective its just 1. 6 X faster 1/25/2010 CS 252 S 10, Lecture 02 19

CPI Computer Performance inst count CPU time = Seconds = Instructions x Program Cycles

CPI Computer Performance inst count CPU time = Seconds = Instructions x Program Cycles Cycle time x Seconds Instruction Cycle Inst Count CPI Clock Rate Program X Compiler X (X) Inst. Set. X X Organization X Technology 1/25/2010 X X CS 252 S 10, Lecture 02 20

Cycles Per Instruction (Throughput) “Average Cycles per Instruction” CPI = (CPU Time * Clock

Cycles Per Instruction (Throughput) “Average Cycles per Instruction” CPI = (CPU Time * Clock Rate) / Instruction Count = Cycles / Instruction Count “Instruction Frequency” 1/25/2010 CS 252 S 10, Lecture 02 21

Example: Calculating CPI bottom up Run benchmark and collect workload characterization (simulate, machine counters,

Example: Calculating CPI bottom up Run benchmark and collect workload characterization (simulate, machine counters, or sampling) Base Machine Op ALU Load Store Branch (Reg / Freq 50% 20% 10% 20% Reg) Cycles 1 2 2 2 Typical Mix of instruction types in program CPI(i). 5. 4. 2. 4 1. 5 (% Time) (33%) (27%) (13%) (27%) Design guideline: Make the common case fast MIPS 1% rule: only consider adding an instruction of it is shown to add 1% performance improvement on reasonable benchmarks. 1/25/2010 CS 252 S 10, Lecture 02 22

Power and Energy • Energy to complete operation (Joules) – Corresponds approximately to battery

Power and Energy • Energy to complete operation (Joules) – Corresponds approximately to battery life – (Battery energy capacity actually depends on rate of discharge) • Peak power dissipation (Watts = Joules/second) – Affects packaging (power and ground pins, thermal design) • di/dt, peak change in supply current (Amps/second) – Affects power supply noise (power and ground pins, decoupling capacitors) 1/25/2010 CS 252 S 10, Lecture 02 23

Peak Power versus Lower Energy Peak A Peak B Power Integrate power curve to

Peak Power versus Lower Energy Peak A Peak B Power Integrate power curve to get energy Time • System A has higher peak power, but lower total energy • System B has lower peak power, but higher total energy 1/25/2010 CS 252 S 10, Lecture 02 24

CS 252 Administrivia • Sign up! Web site is: http: //www. cs. berkeley. edu/~kubitron/cs

CS 252 Administrivia • Sign up! Web site is: http: //www. cs. berkeley. edu/~kubitron/cs 252 • Review: Chapter 1, Appendix A, B, C • CS 152 home page, maybe “Computer Organization and Design (COD)2/e” – If did take a class, be sure COD Chapters 2, 5, 6, 7 are familiar – Copies in Bechtel Library on 2 hour reserve • First two readings are up (look on Lecture page) – Read the assignment carefully, since the requirements vary about what you need to turn in – Submit results to website before class » (will be a link up on handouts page) – You can have 5 total late days on assignments » 10% per day afterwards » Save late days! 1/25/2010 CS 252 S 10, Lecture 02 25

CS 252 Administrivia • Resources for course on web site: – Check out the

CS 252 Administrivia • Resources for course on web site: – Check out the ISCA (International Symposium on Computer Architecture) 25 th year retrospective on web site. Look for “Additional reading” below text book description – Pointers to previous CS 152 exams and resources – Lots of old CS 252 material – Interesting links. Check out the: WWW Computer Architecture Home Page • Size of class seems ok: – I asked Michael David to put everyone on waitlist into class – Check to make sure 1/25/2010 CS 252 S 10, Lecture 02 26

ISA Implementation Review 1/25/2010 CS 252 S 10, Lecture 02 27

ISA Implementation Review 1/25/2010 CS 252 S 10, Lecture 02 27

A "Typical" RISC ISA • • 32 bit fixed format instruction (3 formats) 32

A "Typical" RISC ISA • • 32 bit fixed format instruction (3 formats) 32 32 bit GPR (R 0 contains zero, DP take pair) 3 address, reg arithmetic instruction Single address mode for load/store: base + displacement – no indirection • Simple branch conditions • Delayed branch see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM Power. PC, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3 1/25/2010 CS 252 S 10, Lecture 02 28

Example: MIPS ( MIPS) Register-Register 31 26 25 Op 21 20 Rs 1 16

Example: MIPS ( MIPS) Register-Register 31 26 25 Op 21 20 Rs 1 16 15 Rs 2 11 10 6 5 Rd 0 Opx Register-Immediate 31 26 25 Op 21 20 Rs 1 16 15 Rd immediate 0 Branch 31 26 25 Op Rs 1 21 20 16 15 Rs 2/Opx immediate 0 Jump / Call 31 26 25 Op 1/25/2010 target CS 252 S 10, Lecture 02 0 29

Datapath vs Control Datapath Controller signals Control Points • Datapath: Storage, FU, interconnect sufficient

Datapath vs Control Datapath Controller signals Control Points • Datapath: Storage, FU, interconnect sufficient to perform the desired functions – Inputs are Control Points – Outputs are signals • Controller: State machine to orchestrate operation on the data path 1/25/2010 – Based on desired function and signals CS 252 S 10, Lecture 02 30

Simple Pipelining Review 1/25/2010 CS 252 S 10, Lecture 02 31

Simple Pipelining Review 1/25/2010 CS 252 S 10, Lecture 02 31

5 Steps of MIPS Datapath Execute Addr. Calc Instr. Decode Reg. Fetch Next SEQ

5 Steps of MIPS Datapath Execute Addr. Calc Instr. Decode Reg. Fetch Next SEQ PC Adder 4 Zero? RS 1 RD RD RD MUX Sign Extend MEM/WB Data Memory EX/MEM ALU Imm MUX A <= Reg[IRrs]; B <= Reg[IRrt] ID/EX IR <= mem[PC]; PC <= PC + 4 Reg File IF/ID Memory Address RS 2 Write Back MUX Next PC Memory Access WB Data Instruction Fetch rslt <= A op. IRop B WB <= rslt Reg[IRrd] <= WB 1/25/2010 • Data stationary control – local decode for each instruction phase / pipeline stage CS 252 S 10, Lecture 02 32

Visualizing Pipelining Figure A. 2, Page A 8 Time (clock cycles) 1/25/2010 Ifetch DMem

Visualizing Pipelining Figure A. 2, Page A 8 Time (clock cycles) 1/25/2010 Ifetch DMem Reg ALU O r d e r Ifetch ALU I n s t r. ALU Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Ifetch Reg CS 252 S 10, Lecture 02 Reg DMem Reg 33

Pipelining is not quite that easy! • Limits to pipelining: Hazards prevent next instruction

Pipelining is not quite that easy! • Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle – Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away) – Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock) – Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps). 1/25/2010 CS 252 S 10, Lecture 02 34

One Memory Port/Structural Hazards Figure A. 4, Page A 14 Time (clock cycles) O

One Memory Port/Structural Hazards Figure A. 4, Page A 14 Time (clock cycles) O r d e r 1/25/2010 Instr 2 Instr 3 Instr 4 Ifetch DMem Reg ALU Instr 1 Reg ALU Ifetch ALU Load ALU I n s t r. ALU Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Ifetch Reg Ifetch CS 252 S 10, Lecture 02 Reg Reg DMem Reg 35

One Memory Port/Structural Hazards (Similar to Figure A. 5, Page A 15) Time (clock

One Memory Port/Structural Hazards (Similar to Figure A. 5, Page A 15) Time (clock cycles) Instr 1 O r d e r Instr 2 Stall Reg Ifetch DMem Reg Ifetch Bubble Instr 3 Reg DMem Bubble Ifetch Reg Bubble ALU Ifetch ALU Load ALU I n s t r. ALU Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Bubble DMem Reg How do you “bubble” the pipe? 1/25/2010 CS 252 S 10, Lecture 02 36

Speed Up Equation for Pipelining For simple RISC pipeline, CPI = 1: 1/25/2010 CS

Speed Up Equation for Pipelining For simple RISC pipeline, CPI = 1: 1/25/2010 CS 252 S 10, Lecture 02 37

Example: Dual port vs. Single port • Machine A: Dual ported memory (“Harvard Architecture”)

Example: Dual port vs. Single port • Machine A: Dual ported memory (“Harvard Architecture”) • Machine B: Single ported memory, but its pipelined implementation has a 1. 05 times faster clock rate • Ideal CPI = 1 for both • Loads are 40% of instructions executed Speed. Up. A = Pipeline Depth/(1 + 0) x (clockunpipe/clockpipe) = Pipeline Depth Speed. Up. B = Pipeline Depth/(1 + 0. 4 x 1) x (clockunpipe/(clockunpipe / 1. 05) = (Pipeline Depth/1. 4) x 1. 05 = 0. 75 x Pipeline Depth Speed. Up. A / Speed. Up. B = Pipeline Depth/(0. 75 x Pipeline Depth) = 1. 33 • Machine A is 1. 33 times faster 1/25/2010 CS 252 S 10, Lecture 02 38

Data Hazard on R 1 Time (clock cycles) and r 6, r 1, r

Data Hazard on R 1 Time (clock cycles) and r 6, r 1, r 7 or r 8, r 1, r 9 Ifetch DMem Reg DMem Ifetch Reg ALU sub r 4, r 1, r 3 Reg ALU Ifetch ALU O r d e r add r 1, r 2, r 3 xor r 10, r 11 1/25/2010 WB ALU I n s t r. MEM ALU IF ID/RF EX CS 252 S 10, Lecture 02 Reg Reg DMem Reg 39

Three Generic Data Hazards • Read After Write (RAW) Instr. J tries to read

Three Generic Data Hazards • Read After Write (RAW) Instr. J tries to read operand before Instr. I writes it I: add r 1, r 2, r 3 J: sub r 4, r 1, r 3 • Caused by a “Dependence” (in compiler nomenclature). This hazard results from an actual need for communication. 1/25/2010 CS 252 S 10, Lecture 02 40

Three Generic Data Hazards • Write After Read (WAR) Instr. J writes operand before

Three Generic Data Hazards • Write After Read (WAR) Instr. J writes operand before Instr. I reads it I: sub r 4, r 1, r 3 J: add r 1, r 2, r 3 K: mul r 6, r 1, r 7 • Called an “anti dependence” by compiler writers. This results from reuse of the name “r 1”. • Can’t happen in MIPS 5 stage pipeline because: – All instructions take 5 stages, and – Reads are always in stage 2, and – Writes are always in stage 5 1/25/2010 CS 252 S 10, Lecture 02 41

Three Generic Data Hazards • Write After Write (WAW) Instr. J writes operand before

Three Generic Data Hazards • Write After Write (WAW) Instr. J writes operand before Instr. I writes it. I: sub r 1, r 4, r 3 J: add r 1, r 2, r 3 K: mul r 6, r 1, r 7 • Called an “output dependence” by compiler writers This also results from the reuse of name “r 1”. • Can’t happen in MIPS 5 stage pipeline because: – All instructions take 5 stages, and – Writes are always in stage 5 • Will see WAR and WAW in more complicated pipes 1/25/2010 CS 252 S 10, Lecture 02 42

Forwarding to Avoid Data Hazard or r 8, r 1, r 9 Reg DMem

Forwarding to Avoid Data Hazard or r 8, r 1, r 9 Reg DMem Ifetch Reg ALU and r 6, r 1, r 7 Ifetch DMem ALU sub r 4, r 1, r 3 Reg ALU O r d e r add r 1, r 2, r 3 Ifetch ALU I n s t r. ALU Time (clock cycles) xor r 10, r 11 1/25/2010 CS 252 S 10, Lecture 02 Reg Reg DMem Reg 43

HW Change for Forwarding Next. PC mux MEM/WR EX/MEM ALU mux ID/EX Registers Data

HW Change for Forwarding Next. PC mux MEM/WR EX/MEM ALU mux ID/EX Registers Data Memory mux Immediate What circuit detects and resolves this hazard? 1/25/2010 CS 252 S 10, Lecture 02 44

Forwarding to Avoid LW SW Data Hazard or r 8, r 6, r 9

Forwarding to Avoid LW SW Data Hazard or r 8, r 6, r 9 Reg DMem Ifetch Reg ALU sw r 4, 12(r 1) Ifetch DMem ALU lw r 4, 0(r 1) Reg ALU O r d e r add r 1, r 2, r 3 Ifetch ALU I n s t r. ALU Time (clock cycles) xor r 10, r 9, r 11 1/25/2010 CS 252 S 10, Lecture 02 Reg Reg DMem Reg 45

Data Hazard Even with Forwarding and r 6, r 1, r 7 or 1/25/2010

Data Hazard Even with Forwarding and r 6, r 1, r 7 or 1/25/2010 r 8, r 1, r 9 DMem Ifetch Reg DMem Reg Ifetch CS 252 S 10, Lecture 02 Reg Reg DMem ALU O r d e r sub r 4, r 1, r 6 Reg ALU lw r 1, 0(r 2) Ifetch ALU I n s t r. ALU Time (clock cycles) Reg DMem Reg 46

Data Hazard Even with Forwarding and r 6, r 1, r 7 1/25/2010 or

Data Hazard Even with Forwarding and r 6, r 1, r 7 1/25/2010 or r 8, r 1, r 9 DMem Ifetch Reg Bubble Ifetch Bubble Reg Bubble Ifetch CS 252 S 10, Lecture 02 Reg DMem ALU O r d e r sub r 4, r 1, r 6 Reg ALU lw r 1, 0(r 2) Ifetch ALU I n s t r. ALU Time (clock cycles) Reg DMem 47

Software Scheduling to Avoid Load Hazards Try producing fast code for a = b

Software Scheduling to Avoid Load Hazards Try producing fast code for a = b + c; d = e – f; assuming a, b, c, d , e, and f in memory. Slow code: LW LW ADD SW LW LW SUB SW 1/25/2010 Rb, b Rc, c Ra, Rb, Rc a, Ra Re, e Rf, f Rd, Re, Rf d, Rd Fast code: LW LW LW ADD LW SW SUB SW CS 252 S 10, Lecture 02 Rb, b Rc, c Re, e Ra, Rb, Rc Rf, f a, Ra Rd, Re, Rf d, Rd 48

Reg DMem Ifetch Reg ALU r 6, r 1, r 7 Ifetch DMem ALU

Reg DMem Ifetch Reg ALU r 6, r 1, r 7 Ifetch DMem ALU 18: or Reg ALU 14: and r 2, r 3, r 5 Ifetch ALU 10: beq r 1, r 3, 36 ALU Control Hazard on Branches Three Stage Stall 22: add r 8, r 1, r 9 36: xor r 10, r 11 Reg Reg DMem Reg What do you do with the 3 instructions in between? How do you do it? Where is the “commit”? 1/25/2010 CS 252 S 10, Lecture 02 49

Branch Stall Impact • If CPI = 1, 30% branch, Stall 3 cycles =>

Branch Stall Impact • If CPI = 1, 30% branch, Stall 3 cycles => new CPI = 1. 9! • Two part solution: – Determine branch taken or not sooner, AND – Compute taken branch address earlier • MIPS branch tests if register = 0 or 0 • MIPS Solution: – Move Zero test to ID/RF stage – Adder to calculate new PC in ID/RF stage – 1 clock cycle penalty for branch versus 3 1/25/2010 CS 252 S 10, Lecture 02 50

Pipelined MIPS Datapath Figure A. 24, page A 38 Instruction Fetch Memory Access Write

Pipelined MIPS Datapath Figure A. 24, page A 38 Instruction Fetch Memory Access Write Back Adder MUX Next SEQ PC Next PC Zero? RS 1 RD RD RD MUX Sign Extend MEM/WB Data Memory EX/MEM ALU MUX Imm ID/EX Reg File IF/ID Memory Address RS 2 WB Data 4 Execute Addr. Calc Instr. Decode Reg. Fetch • Interplay of instruction set design and cycle time. 1/25/2010 CS 252 S 10, Lecture 02 51

Four Branch Hazard Alternatives #1: Stall until branch direction is clear #2: Predict Branch

Four Branch Hazard Alternatives #1: Stall until branch direction is clear #2: Predict Branch Not Taken – – – Execute successor instructions in sequence “Squash” instructions in pipeline if branch actually taken Advantage of late pipeline state update 47% MIPS branches not taken on average PC+4 already calculated, so use it to get next instruction #3: Predict Branch Taken – 53% MIPS branches taken on average – But haven’t calculated branch target address in MIPS » MIPS still incurs 1 cycle branch penalty » Other machines: branch target known before outcome 1/25/2010 CS 252 S 10, Lecture 02 52

Four Branch Hazard Alternatives #4: Delayed Branch – Define branch to take place AFTER

Four Branch Hazard Alternatives #4: Delayed Branch – Define branch to take place AFTER a following instruction branch instruction sequential successor 1 sequential successor 2. . . . sequential successorn branch target if taken Branch delay of length n – 1 slot delay allows proper decision and branch target address in 5 stage pipeline – MIPS uses this 1/25/2010 CS 252 S 10, Lecture 02 53

Scheduling Branch Delay Slots A. From before branch add $1, $2, $3 if $2=0

Scheduling Branch Delay Slots A. From before branch add $1, $2, $3 if $2=0 then delay slot becomes B. From branch target sub $4, $5, $6 add $1, $2, $3 if $1=0 then delay slot becomes if $2=0 then add $1, $2, $3 if $1=0 then sub $4, $5, $6 C. From fall through add $1, $2, $3 if $1=0 then delay slot sub $4, $5, $6 becomes add $1, $2, $3 if $1=0 then sub $4, $5, $6 • A is the best choice, fills delay slot & reduces instruction count (IC) • In B, the sub instruction may need to be copied, increasing IC • In B and C, must be okay to execute sub when branch fails 1/25/2010 CS 252 S 10, Lecture 02 54

Delayed Branch • Compiler effectiveness for single branch delay slot: – Fills about 60%

Delayed Branch • Compiler effectiveness for single branch delay slot: – Fills about 60% of branch delay slots – About 80% of instructions executed in branch delay slots useful in computation – About 50% (60% x 80%) of slots usefully filled • Delayed Branch downside: As processor go to deeper pipelines and multiple issue, the branch delay grows and need more than one delay slot – Delayed branching has lost popularity compared to more expensive but more flexible dynamic approaches – Growth in available transistors has made dynamic approaches relatively cheaper 1/25/2010 CS 252 S 10, Lecture 02 55

Evaluating Branch Alternatives Assume 4% unconditional branch, 6% conditional branch untaken, 10% conditional branch

Evaluating Branch Alternatives Assume 4% unconditional branch, 6% conditional branch untaken, 10% conditional branch taken Scheduling Branch CPI speedup v. scheme penalty unpipelined stall Stall pipeline 3 1. 60 3. 1 1. 0 Predict taken 1 1. 20 4. 2 1. 33 Predict not taken 1 1. 14 4. 4 1. 40 Delayed branch 0. 5 1. 10 4. 5 1. 45 1/25/2010 CS 252 S 10, Lecture 02 56

Problems with Pipelining • Exception: An unusual event happens to an instruction during its

Problems with Pipelining • Exception: An unusual event happens to an instruction during its execution – Examples: divide by zero, undefined opcode • Interrupt: Hardware signal to switch the processor to a new instruction stream – Example: a sound card interrupts when it needs more audio output samples (an audio “click” happens if it is left waiting) • Problem: It must appear that the exception or interrupt must appear between 2 instructions (Ii and Ii+1) – The effect of all instructions up to and including Ii is totalling complete – No effect of any instruction after Ii can take place • The interrupt (exception) handler either aborts program or restarts at instruction Ii+1 1/25/2010 CS 252 S 10, Lecture 02 57

Precise Exceptions in Static Pipelines Key observation: architected state only change in memory and

Precise Exceptions in Static Pipelines Key observation: architected state only change in memory and register write stages. 1/25/2010 CS 252 S 10, Lecture 02 58

Summary: Control and Pipelining • • Next time: Read Appendix A Control VIA State

Summary: Control and Pipelining • • Next time: Read Appendix A Control VIA State Machines and Microprogramming Just overlap tasks; easy if tasks are independent Speed Up Pipeline Depth; if ideal CPI is 1, then: • Hazards limit performance on computers: – Structural: need more HW resources – Data (RAW, WAR, WAW): need forwarding, compiler scheduling – Control: delayed branch, prediction • Exceptions, Interrupts add complexity • Next time: Read Appendix C, record bugs online! 1/25/2010 CS 252 S 10, Lecture 02 59