EECS 105 Fall 2003 Lecture 12 MOS Transistor

EECS 105 Fall 2003, Lecture 12: MOS Transistor Models Prof. Niknejad Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Lecture Outline l MOS Transistors (4. 3 – 4. 6) – – Department of EECS I-V curve (Square-Law Model) Small Signal Model (Linear Model) University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Observed Behavior: ID-VGS l l l Current zero for negative gate voltage Current in transistor is very low until the gate voltage crosses the threshold voltage of device (same threshold voltage as MOS capacitor) Current increases rapidly at first and then it finally reaches a point where it simply increases linearly Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Observed Behavior: ID-VDS non-linear resistor region “constant” current resistor region l l l For low values of drain voltage, the device is like a resistor As the voltage is increases, the resistance behaves non-linearly and the rate of increase of current slows Eventually the current stops growing and remains essentially constant (current source) Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad “Linear” Region Current S p+ G D n+ n+ p-type NMOS l l l Inversion layer “channel” If the gate is biased above threshold, the surface is inverted This inverted region forms a channel that connects the drain and gate If a drain voltage is applied positive, electrons will flow from source to drain Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad MOSFET: Variable Resistor l l l Notice that in the linear region, the current is proportional to the voltage Can define a voltage-dependent resistor This is a nice variable resistor, electronically tunable! Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Finding ID = f (VGS, VDS) l Approximate inversion charge QN(y): drain is higher than the source less charge at drain end of channel Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Inversion Charge at Source/Drain Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Average Inversion Charge Source End l l Drain End Charge at drain end is lower since field is lower Simple approximation: In reality we should integrate the total charge minus the bulk depletion charge across the channel Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Drift Velocity and Drain Current “Long-channel” assumption: use mobility to find v Substituting: Inverted Parabolas Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Square-Law Characteristics TRIODE REGION Boundary: what is ID, SAT? SATURATION REGION Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 The Saturation Region Prof. A. Niknejad When VDS > VGS – VTn, there isn’t any inversion charge at the drain … according to our simplistic model Why do curves flatten out? Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Square-Law Current in Saturation Current stays at maximum (where VDS = VGS – VTn = VDS, SAT) Measurement: ID increases slightly with increasing VDS model with linear “fudge factor” Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Pinching the MOS Transistors S p+ Depletion Region l l l D n+ n+ p-type NMOS l G Pinch-Off Point When VDS > VDS, sat, the channel is “pinched” off at drain end (hence the name “pinch-off region”) Drain mobile charge goes to zero (region is depleted), the remaining elecric field is dropped across this high-field depletion region As the drain voltage is increases further, the pinch off point moves back towards source Channel Length Modulation: The effective channel length is thus reduced higher IDS Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Linear MOSFET Model Channel (inversion) charge: neglect reduction at drain Velocity saturation defines VDS, SAT = Esat L = constant Drain current: - vsat / n |Esat| = 104 V/cm, L = 0. 12 m VDS, SAT = 0. 12 V! Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Why Find an Incremental Model? l Signals of interest in analog ICs are often of the form: Fixed Bias Point Small Signal Direct substitution into i. D = f(v. GS, v. DS) is tedious AND doesn’t include charge-storage effects … pretty rough approximation Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Which Operating Region? TRIODE SAT OFF Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Changing One Variable at a Time Square Law Saturation Region Linear Triode Region Slope of Tangent: Incremental current increase Assumption: VDS > VDS, SAT = VGS – VTn (square law) Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad The Transconductance gm Defined as the change in drain current due to a change in the gate-source voltage, with everything else constant Gate Bias Drain Current Bias and Gate Bias Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Output Resistance ro Defined as the inverse of the change in drain current due to a change in the drain-source voltage, with everything else constant Non-Zero Slope Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Evaluating ro Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Total Small Signal Current Transconductance Department of EECS Conductance University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Putting Together a Circuit Model Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Role of the Substrate Potential Need not be the source potential, but VB < VS Effect: changes threshold voltage, which changes the drain current … substrate acts like a “backgate” Q = (VGS, VDS, VBS) Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Backgate Transconductance Result: Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Four-Terminal Small-Signal Model Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad MOSFET Capacitances in Saturation Gate-source capacitance: channel charge is not controlled by drain in saturation. Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Gate-Source Capacitance Cgs Wedge-shaped charge in saturation effective area is (2/3)WL (see H&S 4. 5. 4 for details) Overlap capacitance along source edge of gate (Underestimate due to fringing fields) Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Gate-Drain Capacitance Cgd Not due to change in inversion charge in channel Overlap capacitance Cov between drain and source is Cgd Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Junction Capacitances Prof. A. Niknejad Drain and source diffusions have (different) junction capacitances since VSB and VDB = VSB + VDS aren’t the same Complete model (without interconnects) Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad P-Channel MOSFET Measurement of –IDp versus VSD, with VSG as a parameter: Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Square-Law PMOS Characteristics Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Small-Signal PMOS Model Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad MOSFET SPICE Model Many “levels” … we will use the square-law “Level 1” model See H&S 4. 6 + Spice refs. on reserve for details. Department of EECS University of California, Berkeley