EECS 105 Fall 2004 Lecture 42 Review of

EECS 105 Fall 2004, Lecture 42: Review of active MOSFET circuits Prof. J. S. Smith Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Final Exam l l Covers the course from the beginning Date/Time: SATURDAY, MAY 15, 2004 8 -11 A Location: BECHTEL auditorium One page (Two sides) of notes Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Observed Behavior: ID-VDS non-linear resistor region “constant” current resistor region l l l For low values of drain voltage, the device is like a resistor As the voltage is increases, the resistance behaves non-linearly and the rate of increase of current slows Eventually the current stops growing and remains essentially constant (current source) Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Observed Behavior: ID-VDS non-linear resistor region “constant” current resistor region As the drain voltage increases, the E field across the oxide at the drain end is reduced, and so the charge is less, and the current no longer increases proportionally. As the gate-source voltage is increased, this happens at higher and higher drain voltages. The start of the saturation region is shaped like a parabola Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Finding ID = f (VGS, VDS) l Approximate inversion charge QN(y): drain is higher than the source less charge at drain end of channel Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Inversion Charge at Source/Drain The charge under the gate along the gate, but we are going to make a simple approximation, that the average charge is the average of the charge near the source and drain Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Average Inversion Charge Source End l l l Drain End Charge at drain end is lower since field is lower Notice that this only works if the gate is inverted along its entire length If there is an inversion along the entire gate, it works well because Q is proportional to V everywhere the gate is inverted Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Drift Velocity and Drain Current “Long-channel” assumption: use mobility to find v And now the current is just charge per area, times velocity, times the width: Inverted Parabolas Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Square-Law Characteristics TRIODE REGION Boundary: what is ID, SAT? SATURATION REGION Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 The Saturation Region Prof. J. S. Smith When VDS > VGS – VTn, there isn’t any inversion charge at the drain … according to our simplistic model Why do curves flatten out? Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Square-Law Current in Saturation Current stays at maximum (where VDS = VGS – VTn ) Measurement: ID increases slightly with increasing VDS model with linear “fudge factor” Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith A Simple Circuit: An MOS Amplifier Input signal Supply “Rail” Output signal Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small Signal Analysis l l l Step 1: Find DC operating point. Calculate (estimate) the DC voltages and currents (ignore small signals sources) Substitute the small-signal model of the MOSFET/BJT/Diode and the small-signal models of the other circuit elements. Solve for desired parameters (gain, input impedance, …) Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith A Simple Circuit: An MOS Amplifier Input signal Supply “Rail” Output signal Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Analysis Step 1. Find DC Bias – ignore small-signal source IGS, Q VGS, BIAS was found in Lecture 15 Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Modeling What are the small-signal models of the DC supplies? Shorts! Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Models of Ideal Supplies Small-signal model: short open Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Circuit for Amplifier Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Low-Frequency Voltage Gain Consider first 0 case … capacitors are open-circuits Design Variable Transconductance Design Variables Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Voltage Gain (Cont. ) Substitute transconductance: Output resistance: typical value n= 0. 05 V-1 Voltage gain: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Input and Output Waveforms Output small-signal voltage amplitude: 14 x 25 m. V = 350 Input small-signal voltage amplitude: 25 m. V Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith What Limits the Output Amplitude? 1. v. OUT(t) reaches VSUP or 0 … or 2. MOSFET leaves constant-current region and enters triode region Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Maximum Output Amplitude vout(t)= -2. 18 V cos( t) vs(t) = 152 m. V cos( t) How accurate is the small-signal (linear) model? Significant error in neglecting third term in expansion of i. D = i. D (v. GS) Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith One-Port Models (EECS 40) l A terminal pair across which a voltage and associated current are defined Circuit Block Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Two-Port Models l We assume that input port is linear and that the amplifier is unilateral: – l l Output depends on input but input is independent of output. Output port : depends linearly on the current and voltage at the input and output ports Unilateral assumption is good as long as “overlap” capacitance is small (MOS) Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Two-Port Small-Signal Amplifiers Voltage Amplifier Current Amplifier Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Two-Port Small-Signal Amplifiers Transconductance Amplifier Transresistance Amplifier Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Common-Source Amplifier (again) How to isolate DC level? Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith DC Bias 5 V Neglect all AC signals 2. 5 V Choose IBIAS, W/L Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Load-Line Analysis to find Q Q Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Analysis Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Two-Port Parameters: Find Rin, Rout, Gm Department of EECS Generic Transconductance Amp University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Two-Port CS Model Reattach source and load one-ports: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Maximize Gain of CS Amp l l l Increase the gm (more current) Increase RD (free? Don’t need to dissipate extra power) Limit: Must keep the device in saturation For a fixed current, the load resistor can only be chosen so large To have good swing we’d also like to avoid getting too close to saturation Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Current Source Supply l l Department of EECS Solution: Use a current source! Current independent of voltage for ideal source University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CS Amp with Current Source Supply Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Load Line for DC Biasing Prof. J. S. Smith Both the I-source and the transistor are idealized for DC bias analysis Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Two-Port Parameters From current source supply Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith P-Channel CS Amplifier DC bias: VSG = VDD – VBIAS sets drain current –IDp = ISUP Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Common Gate Amplifier Notice that IOUT must equal -Is Prof. J. S. Smith DC bias: Gain of transistor tends to hold this node at ss ground: low input impedance load for current input current gain=1 Impedance buffer Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CG as a Current Amplifier: Find Ai Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CG Input Resistance At input: Output voltage: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Approximations… l l We have this messy result But we don’t need that much precision. Let’s start approximating: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Department of EECS CG Output Resistance Prof. J. S. Smith University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CG Output Resistance Substituting vs = it. RS The output resistance is (vt / it)|| roc Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Approximating the CG Rout Prof. J. S. Smith The exact result is complicated, so let’s try to make it simpler: Assuming the source resistance is less than ro, Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CG Two-Port Model Function: a current buffer • Low Input Impedance • High Output Impedance Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Common-Drain Amplifier In the common drain amp, the output is taken from a terminal of which the current is a sensitive function Weak IDS dependence Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CD Voltage Gain Note vgs = vt – vout Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CD Voltage Gain (Cont. ) KCL at source node: Voltage gain (for v. SB not zero): Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CD Output Resistance Sum currents at output (source) node: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CD Output Resistance (Cont. ) ro || roc is much larger than the inverses of the transconductances ignore Function: a voltage buffer • High Input Impedance • Low Output Impedance Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Voltage and current gain Current tracks input voltage tracks input Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Bias sensitivity l l l When a transistor biasing circuit is designed, it is important to realize that the characteristics of the transistor can vary widely, and that passive components vary significantly also. Biasing circuits must therefore be designed to produce a usable bias without counting on specific values for these components. One example is a BJT base bias in a CE amp. A slight change in the base-emitter voltage makes a very large difference in the quiescent point. The insertion of a resistor at the emitter will improve sensitivity. Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Insensitivity to transistor parameters l Most of the circuit parameters are independent of variation of the transistor parameters, and depend only on resistance ratios. That is often a design goal, but in integrated circuits we will not want to use so many resistors. Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith NMOS pullup l Rather than using a big (and expensive) resistor, let’s look at a NMOS transistor as an active pullup +V device Note that when the transistor is connected this way, it is not an amplifier, it is a two terminal device. When the gate is connected to the drain of this NMOS device, it will be in saturation, so we get the equation for the drain current: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small signal model l So we have: l The N channel MOSFET’s transconductance is: l And so the small signal model for this device will be a resistor with a resistance: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith IV for NMOS pull-up l The I-V characteristic of this pull-up device: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Active Load l We can use this as the pullup device for an NMOS common source amplifier: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Active Load Since I 2=I 1 we have: And since: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Behavior l l l If the output voltage goes higher than one threshold below VDD, transistor 2 goes into cutoff and the amplifier will clip. If the output goes too low, then transistor 1 will fall out of the saturation mode. Within these limitations, this stage gives a good linear amplification. Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CMOS Diode Connected Transistor l l l Department of EECS Short gate/drain of a transistor and pass current through it Since VGS = VDS, the device is in saturation since VDS > VGS-VT Since FET is a square-law (or weaker) device, the I-V curve is very soft compared to PN junction diode University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Diode Equivalent Circuit: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith The Integrated “Current Mirror” l l l High Res Low Resis l l Department of EECS M 1 and M 2 have the same VGS If we neglect CLM (λ=0), then the drain currents are equal Since λ is small, the currents will nearly mirror one another even if Vout is not equal to VGS 1 We say that the current IREF is mirrored into i. OUT Notice that the mirror works for small and large signals! University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Current Mirror as Current Sink l l The output current of M 2 is only weakly dependent on v. OUT due to high output resistance of FET M 2 acts like a current source to the rest of the circuit Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Resistance of I-Source Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Improved Current Sources Prof. J. S. Smith Goal: increase roc Approach: look at amplifier output resistance results … to see topologies that boost resistance Looks like the output impedance of a commonsource amplifier with source degeneration Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Effect of Source Degeneration l l Equivalent resistance loading gate is dominated by the diode resistance … assume this is a small impedance Output impedance is boosted by factor Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Cascode (or Stacked) Current Source Insight: VGS 2 = constant AND VDS 2 = constant Small-Signal Resistance roc: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Drawback of Cascode I-Source Minimum output voltage to keep both transistors in saturation: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Current Sinks and Sources Sink: output current goes to ground Department of EECS Prof. J. S. Smith Source: output current comes from voltage supply University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Current Mirrors We only need one reference current to set up all the current sources and sinks needed for a multistage amplifier. Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Summary of Cascaded Amplifiers General goals: 1. Boost the gain (except for buffers) 2. Improve frequency response 3. Optimize the input and output resistances: 4. Voltage: Rin Rout Current: Transconductance: Transresistance: Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Start: Two-Stage Voltage Amplifier • Use two-port models to explore whether the combination “works” CS 2 CS 1, 2 Results of new 2 -port: Rin = Rin 1, Rout = Rout 2 Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Cascading stages CS 1 CS 2 CD 3 Input resistance: Voltage gain (2 -port parameter): Output resistance: Department of EECS University of California, Berkeley