ECE 645 Lecture 3 ConditionalSum Adders and Parallel

ECE 645: Lecture 3 Conditional-Sum Adders and Parallel Prefix Network Adders FPGA Optimized Adders

Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 7. 4, Conditional-Sum Adder Chapter 6. 4, Carry Determination as Prefix Computation Chapter 6. 5, Alternative Parallel Prefix Networks

Add-Multiplex Carry Select Adder

Two-level k-bit Carry Select Adder

Add-Multiplex (AAM) Carry Select Adder + stands for the Ripple Carry Adder CCC stands for the Carry Computation Circuit CR stands for the Carry Recovery Circuit

Carry Computation Circuit

Carry Recovery Circuit

Carry & Control Logic in Virtex 4

Carry & Control Logic in Virtex 5

Homework 2 - Bonus Analytical Problem: Find analytically an optimal value of the word size, w, for which a 1024 -bit AAM Carry Select Adder has the smallest latency. Implementation Problem: Find experimentally an optimal value of the word size, w, for which a 1024 -bit AAM Carry Select Adder has the smallest latency. 10

Conditional-Sum Adders

One-level k-bit Carry-Select Adder

Two-level k-bit Carry Select Adder

Conditional Sum Adder • Extension of carry-select adder • Carry select adder • • One-level using k/2 -bit adders Two-level using k/4 -bit adders Three-level using k/8 -bit adders Etc. • Assuming k is a power of two, eventually have an extreme where there are log 2 klevels using 1 -bit adders • This is a conditional sum adder 14

Conditional Sum Adder: Top-Level Block for One Bit Position 15

Three Levels of a Conditional Sum Adder xi+3 yi+3 xi+2 yi+2 xi yi xi+1 yi+1 branch point 1 -bit conditional sum block 2 c=1 c=0 2 1 1 2 2 2 1 1 c=0 3 c=1 3 2 2 c=1 3 1+1 1 c=0 3 1 1 2+1 2 2 3 3 5 c=1 concatenation 5 c=0 4+1 block carry-in determines selection 16

16 -Bit Conditional Sum Adder Example 17

Conditional Sum Adder Metrics 18

Parallel Prefix Network Adders

Parallel Prefix Network Adders Basic component - Carry operator (1) g p B” B’ B g” p” g’ p’ g = g” + g’p” p = p’p” (g, p) = (g’, p’) ¢ (g”, p”) = (g” + g’p”, p’p”) 20

Parallel Prefix Network Adders Basic component - Carry operator (2) g p overlap okay! B” B’ B g” p” g’ p’ g = g” + g’p” p = p’p” (g, p) = (g’, p’) ¢ (g”, p”) = (g” + g’p”, p’p”) 21

Properties of the carry operator ¢ Associative [(g 1, p 1) ¢ (g 2, p 2)] ¢ (g 3, p 3) = (g 1, p 1) ¢ [(g 2, p 2) ¢ (g 3, p 3)] Not commutative (g 1, p 1) ¢ (g 2, p 2) ¢ (g 1, p 1) 22

Parallel Prefix Network Adders Major concept Given: (g 0, p 0) (g 1, p 1) (g 2, p 2) …. (gk-1, pk-1) Find: (g[0, 0], p[0, 0]) (g[0, 1], p[0, 1]) (g[0, 2], p[0, 2]) … (g[0, k-1], p[0, k-1]) ci = g[0, i-1] + c 0 p[0, i-1] block generate from index 0 to k-1 23

Similar to Parallel Prefix Sum Problem Given: x 0 Find: x 1 x 2 … x 0+x 1+x 2 … xk-1 x 0+x 1+x 2+ …+ xk-1 Parallel Prefix Adder Problem Given: x 0 x 1 x 2 … Find: x 0 ¢ x 1 ¢ x 2 … xk-1 x 0 ¢ x 1 ¢ x 2 ¢ … ¢ xk-1 where xi = (gi, pi) 24

Parallel Prefix Sums Network I 25

Parallel Prefix Sums Network II (Brent -Kung) 26

8 -bit Brent-Kung Parallel Prefix Network 27

4 -bit Brent-Kung Parallel Prefix Network x 7’ x 5’ x 3’ x 1’ 2 –bit B-K PPN s 7’ s 5’ s 3’ s 1’ 28

8 -bit Brent-Kung Parallel Prefix Network Adder 29

Critical Path GP c C S gi = xi yi pi = xi yi 1 gate delay g = g” + g’ p” p = p’ p” 2 gate delays ci+1 = g[0, i] + c 0 p[0, i] 2 gate delays si = p i c i 1 gate delay 30

Brent-Kung Parallel Prefix Graph for 16 Inputs 31

Kogge-Stone Parallel Prefix Graph for 16 Inputs 32

Parallel Prefix Network Adders Comparison of architectures Hybrid Network 2 Kogge-Stone Brent-Kung Delay(k) 2 log 2 k - 2 log 2 k+1 log 2 k Cost(k) 2 k - 2 - log 2 k k/2 log 2 k k log 2 k - k + 1 Delay(16) 6 5 4 Cost(16) 26 32 49 Delay(32) 8 6 5 Cost(32) 57 80 129 33

Latency vs. Area Tradeoff 34

Hybrid Brent-Kung/Kogge-Stone Parallel Prefix Graph for 16 Inputs 35

Parallel Prefix Sums Network I 36

Parallel Prefix Sums Network I – Cost (Area) Analysis Cost = C(k) = 2 C(k/2) + k/2 = = 2 [2 C(k/4) + k/4] + k/2 = 4 C(k/4) + k/2 = = …. = = 2 log 2 k-1 C(2) + k/2 (log 2 k-1) = = k/2 log 2 k C(2) = 1 Example: C(16) = 2 C(8) + 8 = 2[2 C(4) + 4] + 8 = = 4 C(4) + 16 = 4 [2 C(2) + 2] + 16 = = 8 C(2) + 24 = 8 + 24 = 32 = (16/2) log 2 16 37

Parallel Prefix Sums Network I – Delay Analysis Delay = D(k) = D(k/2) + 1 = = [D(k/4) + 1] + 1 = D(k/4) + 1 = = …. = = log 2 k D(2) = 1 Example: D(16) = D(8) + 1 = [D(4) + 1] + 1 = = D(4) + 2 = [D(2) + 1] + 2 = = 4 = log 2 16 38

Parallel Prefix Sums Network II (Brent -Kung) 39

Parallel Prefix Sums Network II – Cost (Area) Analysis Cost = C(k) = C(k/2) + k-1 = = [C(k/4) + k/2 -1] + k-1 = C(k/4) + 3 k/2 - 2 = = …. = = C(2) + (2 k - 2 k/2(log 2 k-1)) - (log 2 k-1) = = 2 k - 2 - log 2 k C(2) = 1 Example: C(16) = C(8) + 16 -1 = [C(4) + 8 -1] + 16 -1 = = C(2) + 4 -1 + 24 -2 = 1 + 28 - 3 = 26 = 2· 16 - 2 - log 216 40

Parallel Prefix Sums Network II – Delay Analysis Delay = D(k) = D(k/2) + 2 = = [D(k/4) + 2] + 2 = D(k/4) + 2 = = …. = = 2 log 2 k - 1 D(2) = 1 Example: D(16) = D(8) + 2 = [D(4) + 2] + 2 = = D(4) + 4 = [D(2) + 2] + 4 = = 7 = 2 log 2 16 - 1 41

High-Radix Parallel Prefix Network Adders (GMU CERG Research)

Traditional Parallel-Prefix Network Adder

Kogge-Stone Parallel-Prefix Network

Brent-Kung Parallel-Prefix Network

High-Radix Parallel-Prefix Network Adder

Generate-Propagate-Sum (GPS) Unit

Sum Unit

Modular Addition

High-Radix Parallel-Prefix Network Modular Adder

Test Circuit for Benchmarking Adders and Modular Adders