Lec 17 ADDERS ece 407507 EE 141 Digital

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Lec 17 : ADDERS ece 407/507 © EE 141 Digital Integrated Circuits 2 nd

Lec 17 : ADDERS ece 407/507 © EE 141 Digital Integrated Circuits 2 nd 1 Arithmetic Circuits

Outline q Introduction to Adders q Adder Design q Types of Adders q Design

Outline q Introduction to Adders q Adder Design q Types of Adders q Design Aspects q Discussion on Lab 4 © EE 141 Digital Integrated Circuits 2 nd 2 Arithmetic Circuits

Adders © EE 141 Digital Integrated Circuits 2 nd 3 Arithmetic Circuits

Adders © EE 141 Digital Integrated Circuits 2 nd 3 Arithmetic Circuits

Full-Adder © EE 141 Digital Integrated Circuits 2 nd 4 Arithmetic Circuits

Full-Adder © EE 141 Digital Integrated Circuits 2 nd 4 Arithmetic Circuits

The Binary Adder © EE 141 Digital Integrated Circuits 2 nd 5 Arithmetic Circuits

The Binary Adder © EE 141 Digital Integrated Circuits 2 nd 5 Arithmetic Circuits

Express Sum and Carry as a function of P, G, D Define 3 new

Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A Å B Delete = A B Can also derive expressions for S and Co based on D and P Note that we will be sometimes using an alternate definition for Propagate (P) = A + B © EE 141 Digital Integrated Circuits 2 nd 6 Arithmetic Circuits

The Ripple-Carry Adder Worst case delay linear with the number of bits td =

The Ripple-Carry Adder Worst case delay linear with the number of bits td = O(N) tadder = (N-1)tcarry + tsum Goal: Make the fastest possible carry path circuit © EE 141 Digital Integrated Circuits 2 nd 7 Arithmetic Circuits

Complimentary Static CMOS Full Adder 28 Transistors © EE 141 Digital Integrated Circuits 2

Complimentary Static CMOS Full Adder 28 Transistors © EE 141 Digital Integrated Circuits 2 nd 8 Arithmetic Circuits

Inversion Property © EE 141 Digital Integrated Circuits 2 nd 9 Arithmetic Circuits

Inversion Property © EE 141 Digital Integrated Circuits 2 nd 9 Arithmetic Circuits

Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property © EE 141 Digital

Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property © EE 141 Digital Integrated Circuits 2 nd 10 Arithmetic Circuits

A Better Structure: The Mirror Adder © EE 141 Digital Integrated Circuits 2 nd

A Better Structure: The Mirror Adder © EE 141 Digital Integrated Circuits 2 nd 11 Arithmetic Circuits

Mirror Adder Stick Diagram © EE 141 Digital Integrated Circuits 2 nd 12 Arithmetic

Mirror Adder Stick Diagram © EE 141 Digital Integrated Circuits 2 nd 12 Arithmetic Circuits

The Mirror Adder • The NMOS and PMOS chains are completely symmetrical. A maximum

The Mirror Adder • The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carrygeneration circuitry. • When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important. • The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. • The transistors connected to Ci are placed closest to the output. • Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size. © EE 141 Digital Integrated Circuits 2 nd 13 Arithmetic Circuits

Transmission Gate Full Adder © EE 141 Digital Integrated Circuits 2 nd 14 Arithmetic

Transmission Gate Full Adder © EE 141 Digital Integrated Circuits 2 nd 14 Arithmetic Circuits

Manchester Carry Chain © EE 141 Digital Integrated Circuits 2 nd 15 Arithmetic Circuits

Manchester Carry Chain © EE 141 Digital Integrated Circuits 2 nd 15 Arithmetic Circuits

Manchester Carry Chain © EE 141 Digital Integrated Circuits 2 nd 16 Arithmetic Circuits

Manchester Carry Chain © EE 141 Digital Integrated Circuits 2 nd 16 Arithmetic Circuits

Manchester Carry Chain Stick Diagram © EE 141 Digital Integrated Circuits 2 nd 17

Manchester Carry Chain Stick Diagram © EE 141 Digital Integrated Circuits 2 nd 17 Arithmetic Circuits

Carry-Bypass Adder Also called Carry-Skip © EE 141 Digital Integrated Circuits 2 nd 18

Carry-Bypass Adder Also called Carry-Skip © EE 141 Digital Integrated Circuits 2 nd 18 Arithmetic Circuits

Carry-Bypass Adder (cont. ) tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry +

Carry-Bypass Adder (cont. ) tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum © EE 141 Digital Integrated Circuits 2 nd 19 Arithmetic Circuits

Carry Ripple versus Carry Bypass © EE 141 Digital Integrated Circuits 2 nd 20

Carry Ripple versus Carry Bypass © EE 141 Digital Integrated Circuits 2 nd 20 Arithmetic Circuits

Carry-Select Adder © EE 141 Digital Integrated Circuits 2 nd 21 Arithmetic Circuits

Carry-Select Adder © EE 141 Digital Integrated Circuits 2 nd 21 Arithmetic Circuits

Carry Select Adder: Critical Path © EE 141 Digital Integrated Circuits 2 nd 22

Carry Select Adder: Critical Path © EE 141 Digital Integrated Circuits 2 nd 22 Arithmetic Circuits

Linear Carry Select © EE 141 Digital Integrated Circuits 2 nd 23 Arithmetic Circuits

Linear Carry Select © EE 141 Digital Integrated Circuits 2 nd 23 Arithmetic Circuits

Square Root Carry Select © EE 141 Digital Integrated Circuits 2 nd 24 Arithmetic

Square Root Carry Select © EE 141 Digital Integrated Circuits 2 nd 24 Arithmetic Circuits

Adder Delays - Comparison © EE 141 Digital Integrated Circuits 2 nd 25 Arithmetic

Adder Delays - Comparison © EE 141 Digital Integrated Circuits 2 nd 25 Arithmetic Circuits

Look. Ahead - Basic Idea © EE 141 Digital Integrated Circuits 2 nd 26

Look. Ahead - Basic Idea © EE 141 Digital Integrated Circuits 2 nd 26 Arithmetic Circuits

Look-Ahead: Topology Expanding Lookahead equations: All the way: © EE 141 Digital Integrated Circuits

Look-Ahead: Topology Expanding Lookahead equations: All the way: © EE 141 Digital Integrated Circuits 2 nd 27 Arithmetic Circuits

Logarithmic Look-Ahead Adder © EE 141 Digital Integrated Circuits 2 nd 28 Arithmetic Circuits

Logarithmic Look-Ahead Adder © EE 141 Digital Integrated Circuits 2 nd 28 Arithmetic Circuits

Carry Lookahead Trees Can continue building the tree hierarchically. © EE 141 Digital Integrated

Carry Lookahead Trees Can continue building the tree hierarchically. © EE 141 Digital Integrated Circuits 2 nd 29 Arithmetic Circuits

About Lab 4 q Design a 4 bit carry Look Ahead Adder q Measure

About Lab 4 q Design a 4 bit carry Look Ahead Adder q Measure Propagation Delay q Layout q Simulations q Analysis © EE 141 Digital Integrated Circuits 2 nd 30 Arithmetic Circuits

Layout q Focus on a Modular design ex: Design of propagate and generate blocks

Layout q Focus on a Modular design ex: Design of propagate and generate blocks q Test individual modules First. Go ahead only if each module works. Modules like § § § Propagate Generate Carry Generator Hint: Use the gates designed in previous labs. Take care of area of the designs © EE 141 Digital Integrated Circuits 2 nd 31 Arithmetic Circuits

Simulations q Individual Blocks like Propagate, Generate, carry generator need to be simulated. q

Simulations q Individual Blocks like Propagate, Generate, carry generator need to be simulated. q Measure the propagation delay of each of the blocks, Area etc. q Simulation of the complete Design EACH STEP CARRYS POINTS!!!!! © EE 141 Digital Integrated Circuits 2 nd 32 Arithmetic Circuits

Analysis q Comment on the design considerations. q Sizing of the Transistors q Reducing

Analysis q Comment on the design considerations. q Sizing of the Transistors q Reducing Capacitance q Identify the critical path q Design Problems and Solutions. © EE 141 Digital Integrated Circuits 2 nd 33 Arithmetic Circuits

What is to be turned in… q. A good report (need not be highly

What is to be turned in… q. A good report (need not be highly detailed) covering the above aspects. q When…. Last day of Classes!!!! q Advice: Start your work soon. Things are not as easy as they seem. © EE 141 Digital Integrated Circuits 2 nd 34 Arithmetic Circuits

Questions © EE 141 Digital Integrated Circuits 2 nd 35 Arithmetic Circuits

Questions © EE 141 Digital Integrated Circuits 2 nd 35 Arithmetic Circuits