CS 152 Computer Architecture and Engineering Lecture 15

CS 152 Computer Architecture and Engineering Lecture 15 Advanced pipelining/Compiler Scheduling October 24, 2001 John Kubiatowicz (http. cs. berkeley. edu/~kubitron) lecture slides: http: //www-inst. eecs. berkeley. edu/~cs 152/ 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 1

Review: Pipelining • Key to pipelining: smooth flow – Making all instructions the same length can increase performance! • Hazards limit performance – Structural: need more HW resources – Data: need forwarding, compiler scheduling – Control: early evaluation & PC, delayed branch, prediction • Data hazards must be handled carefully: – RAW (Read After Write) data hazards handled by forwarding – WAW (Write After Write) and WAR (Write After Read) hazards don’t exist in 5 stage pipeline • MIPS I instruction set architecture made pipeline visible (delayed branch, delayed load) – Change in programmer semantics to make hardware simpler 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 2

Recap: Data Hazards I Fet ch DCD Mem. Op. Fetch IFetch Structural Hazard I Fet ch DCD Op. Fetch Jump IFetch IF DCD EX IF Mem WB DCD EX IF Store °°° Control Hazard °°° RAW (read after write) Data Hazard Mem WB DCD EX Mem WB IF DCD IF 10/24/01 DCD Exec DCD OF ©UCB Fall 2001 WAW Data Hazard (write after write) OF Ex RS Ex Mem WAR Data Hazard (write after read) CS 152 / Kubiatowicz Lec 15. 3

Recap: Data Stationary Control • The Main Control generates the control signals during Reg/Dec – Control signals for Exec (Ext. Op, ALUSrc, . . . ) are used 1 cycle later – Control signals for Mem (Mem. Wr Branch) are used 2 cycles later – Control signals for Wr (Memto. Reg Mem. Wr) are used 3 cycles later Reg/Dec Mem. Wr Branch Memto. Reg. Wr 10/24/01 Reg. Dst Mem. Wr Branch Memto. Reg. Wr ©UCB Fall 2001 Mem. Wr Branch Memto. Reg. Wr Wr Mem/Wr Register Reg. Dst Ext. Op ALUSrc ALUOp Mem Ex/Mem Register Main Control ID/Ex Register IF/ID Register Ext. Op ALUSrc ALUOp Exec Memto. Reg. Wr CS 152 / Kubiatowicz Lec 15. 4

Review: Resolve RAW by “forwarding” (or bypassing) IAU npc I mem Regs op rw rs rt Forward mux B A im PC n op rw alu S n op rw D mem m Regs 10/24/01 • Detect nearest valid write op operand register and forward into op latches, bypassing remainder of the pipe • Increase muxes to add paths from pipeline registers • Data Forwarding = Data Bypassing n op rw ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 5

Question: Critical Path? ? ? • Bypass path is invariably trouble • Options? Regs PC Sel Forward mux Equal B A alu S D mem im – Make logic really fast – Move forwarding after muxes » Problem: screws up branches that require forwarding! » Use same tricks as “carry-skip” adder to fix this? » This option may just push delay around…. ! – Insert an extra cycle for branches that need forwarding? » Or: hit common case of forwarding from EX stage and stall forward from memory? m Regs 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 6

What about Interrupts, Traps, Faults? • External Interrupts: – Allow pipeline to drain, Fill with NOPs – Load PC with interrupt address • Faults (within instruction, restartable) – Force trap instruction into IF – disable writes till trap hits WB – must save multiple PCs or PC + state • Recall: Precise Exceptions State of the machine is preserved as if program executed up to the offending instruction – All previous instructions completed – Offending instruction and all following instructions act as if they have not even started – Same system code will work on different implementations 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 7

Exception/Interrupts: Implementation questions 5 instructions, executing in 5 different pipeline stages! • Who caused the interrupt? Stage Problem interrupts occurring IF Page fault on instruction fetch; misaligned memory access; memory protection violation ID Undefined or illegal opcode EX Arithmetic exception MEM Page fault on data fetch; misaligned memory access; memory protection violation; memory error • How do we stop the pipeline? How do we restart it? • Do we interrupt immediately or wait? • How do we sort all of this out to maintain preciseness? 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 8

Exception Handling IAU npc I mem Regs B A detect bad instruction address lw $2, 20($5) im n op rw PC Excp detect bad instruction Excp detect overflow alu S Excp detect bad data address D mem m 10/24/01 Regs Excp Allow exception to take effect ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 9

Another look at the exception problem Time Bad Inst TLB fault Overflow IFetch Dcd Exec IFetch Dcd Program Flow Data TLB Mem WB Exec Mem IFetch Dcd WB • Use pipeline to sort this out! – Pass exception status along with instruction. – Keep track of PCs for every instruction in pipeline. – Don’t act on exception until it reache WB stage • Handle interrupts through “faulting noop” in IF stage • When instruction reaches end of MEM stage: – Save PC EPC, Interrupt vector addr PC – Turn all instructions in earlier stages into noops! 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 10

Resolution: Freeze above & Bubble Below IAU npc I mem Regs op rw rs rt freeze PC bubble B A im n op rw alu S n op rw • Flush accomplished by setting “invalid” bit in pipeline D mem m n op rw Regs 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 11

FYI: MIPS R 3000 clocking discipline phi 1 phi 2 • 2 phase non overlapping clocks • Pipeline stage is two (level sensitive) latches phi 1 phi 2 phi 1 Edge-triggered 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 12

MIPS R 3000 Instruction Pipeline Decode Reg. Read Inst Fetch TLB I Cache RF ALU / E. A Memory Operation E. A. TLB Write Reg WB D Cache Resource Usage TLB I cache RF WB ALUALU D Cache Write in phase 1, read in phase 2 => eliminates bypass from WB 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 13

Recall: Data Hazard on r 1 Time (clock cycles) IF Reg Dm Im Reg ALU or r 8, r 1, r 9 WB ALU and r 6, r 1, r 7 MEM ALU O r d e r sub r 4, r 1, r 3 Im EX ALU I n s t r. add r 1, r 2, r 3 ID/RF xor r 10, r 11 Reg Reg Dm Reg With MIPS R 3000 pipeline, no need to forward from WB stage 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 14

MIPS R 3000 Multicycle Operations Use control word of local stage to step through multicycle operation op Rd Ra Rb Stall stages above multicycle operation in the pipeline mul Rd Ra Rb Rd A B Drain (bubble) stages below it Alternatively, launch multiply/divide to autonomous unit, only stall pipe if attempt to get result before ready R Rd T This means stall mflo/mfhi in decode stage if multiply/divide still executing Extra credit in Lab 5 does this to reg file Ex: Multiply, Divide, Cache Miss 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 15

Is CPI = 1 for our pipeline? • Remember that CPI is an “Average # cycles/inst IFetch Dcd Exec IFetch Dcd Mem WB Exec Mem IFetch Dcd WB • CPI here is 1, since the average throughput is 1 instruction every cycle. • What if there are stalls or multi cycle execution? • Usually CPI > 1. How close can we get to 1? ? 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 16

Recall: Compute CPI? • Start with Base CPI • Add stalls • Suppose: – – CPIbase=1 Freqbranch=20%, freqload=30% Suppose branches always cause 1 cycle stall Loads cause a 100 cycle stall 1% of time • Then: CPI = 1 + (1 0. 20)+(100 0. 30 0. 01)=1. 5 • Multicycle? Could treat as: CPIstall=(CYCLES CPIbase) freqinst 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 17

Administrivia • Get moving on Lab 5! – This lab is even harder than Lab 4. – Trickier to debug…! – Start with unpipelined version? » Interesting thought… May or may not help – Division of labor due tonight at Midnight! • Dynamic scheduling techniques discussed in the Other Hennessy & Patterson book: – “Computer Architecture: A Quantitative Approach” – Chapter 4 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 18

Administrivia: Be careful about clock edges in lab 5! D Reg. File Data Mem B M Mem Access PC Next PC Equal IRmem WB Ctrl Exec S IRwb IRex A Mem Ctrl Dcd Ctrl Reg File IR Inst. Mem Valid • Since Register file has edge triggered write: – Must have everything set up at end of memory stage – This means that “M” register here is not necessary! 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 19

Case Study: MIPS R 4000 (200 MHz) • 8 Stage Pipeline: – IF–first half of fetching of instruction; PC selection happens here as well as initiation of instruction cache access. – IS–second half of access to instruction cache. – RF–instruction decode and register fetch, hazard checking and also instruction cache hit detection. – EX–execution, which includes effective address calculation, ALU operation, and branch target computation and condition evaluation. – DF–data fetch, first half of access to data cache. – DS–second half of access to data cache. – TC–tag check, determine whether the data cache access hit. – WB–write back for loads and register operations. • 8 Stages: What is impact on Load delay? Branch delay? Why? 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 20

Case Study: MIPS R 4000 IF IS IF RF IS IF EX RF IS IF DS DF EX RF IS IF TC DS DF EX RF IS IF WB TC DS DF EX RF IS IF IF THREE Cycle Branch Latency (conditions evaluated during EX phase) IS IF RF IS IF EX RF IS IF DS DF EX RF IS IF TC DS DF EX RF IS IF WB TC DS DF EX RF IS IF TWO Cycle Load Latency Delay slot plus two stalls Branch likely cancels delay slot if not taken 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 21

MIPS R 4000 Floating Point • FP Adder, FP Multiplier, FP Divider • Last step of FP Multiplier/Divider uses FP Adder HW • 8 kinds of stages in FP units: Stage Functional unit Description A FP adder Mantissa ADD stage D FP divider Divide pipeline stage E FP multiplier Exception test stage M FP multiplier First stage of multiplier N FP multiplier Second stage of multiplier R FP adder Rounding stage S FP adder Operand shift stage U Unpack FP numbers 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 22

MIPS FP Pipe Stages FP Instr 1 … Add, Subtract Multiply U Divide U D+R, A, R Square root Negate U Absolute value FP compare Stages: M N R S U 10/24/01 2 3 4 5 6 7 U E+M A S+A M R A+R M D 28 R+S M … N D+A N+A R D+R, D+A, U S U U E (A+R)108 … A R S A R First stage of multiplier Second stage of multiplier Rounding stage Operand shift stage Unpack FP numbers ©UCB Fall 2001 A D E 8 Mantissa ADD stage Divide pipeline stage Exception test stage CS 152 / Kubiatowicz Lec 15. 23

R 4000 Performance • Not ideal CPI of 1: – FP structural stalls: Not enough FP hardware (parallelism) – FP result stalls: RAW data hazard (latency) – Branch stalls (2 cycles + unfilled slots) – Load stalls (1 or 2 clock cycles) 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 24

Can we somehow make CPI closer to 1? • Let’s assume full pipelining: – If we have a 4 cycle instruction, then we need 3 instructions between a producing instruction and its use: multf $F 0, $F 2, $F 4 delay 1 delay 2 delay 3 addf $F 6, $F 10, $F 0 Earliest forwarding for 4 -cycle instructions Earliest forwarding for 1 -cycle instructions Fetch Decode addf 10/24/01 Ex 2 Ex 3 delay 2 delay 1 ©UCB Fall 2001 Ex 4 WB multf CS 152 / Kubiatowicz Lec 15. 25

FP Loop: Where are the Hazards? Loop: LD ADDD SD SUBI BNEZ NOP F 0, 0(R 1) ; F 0=vector element F 4, F 0, F 2 ; add scalar from F 2 0(R 1), F 4 ; store result R 1, 8 ; decrement pointer 8 B (DW) R 1, Loop ; branch R 1!=zero ; delayed branch slot Instruction producing result FP ALU op Load double Integer op • 10/24/01 Instruction using result Another FP ALU op Store double Integer op Latency in clock cycles 3 2 1 0 0 Where are the stalls? ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 26

FP Loop Showing Stalls 1 Loop: LD F 0, 0(R 1) 2 stall 3 ADDD F 4, F 0, F 2 4 stall 5 stall 6 SD 0(R 1), F 4 7 SUBI R 1, 8 8 BNEZ R 1, Loop 9 stall Instruction producing result FP ALU op Load double ; F 0=vector element ; add scalar in F 2 ; store result ; decrement pointer 8 B (DW) ; branch R 1!=zero ; delayed branch slot Instruction using result Another FP ALU op Store double FP ALU op Latency in clock cycles 3 2 1 • 9 clocks: Rewrite code to minimize stalls? 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 27

Revised FP Loop Minimizing Stalls 1 Loop: LD F 0, 0(R 1) 2 stall 3 ADDD F 4, F 0, F 2 4 SUBI R 1, 8 5 BNEZ R 1, Loop 6 SD 8(R 1), F 4 ; delayed branch ; altered when move past SUBI Swap BNEZ and SD by changing address of SD Instruction producing result FP ALU op Load double Instruction using result Another FP ALU op Store double FP ALU op Latency in clock cycles 3 2 1 6 clocks: Unroll loop 4 times code to make faster? 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 28

Unroll Loop Four Times (straightforward way) 1 Loop: LD 2 ADDD 3 SD 4 LD 5 ADDD 6 SD 7 LD 8 ADDD 9 SD 10 LD 11 ADDD 12 SD 13 SUBI 14 BNEZ 15 NOP F 0, 0(R 1) F 4, F 0, F 2 0(R 1), F 4 F 6, -8(R 1) F 8, F 6, F 2 -8(R 1), F 8 F 10, -16(R 1) F 12, F 10, F 2 -16(R 1), F 12 F 14, -24(R 1) F 16, F 14, F 2 -24(R 1), F 16 R 1, #32 R 1, LOOP 1 cycle stall 2 cycles stall ; drop SUBI & BNEZ Rewrite loop to minimize stalls? ; drop SUBI & BNEZ ; alter to 4*8 15 + 4 x (1+2) = 27 clock cycles, or 6. 8 per iteration Assumes R 1 is multiple of 4 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 29

Unrolled Loop That Minimizes Stalls 1 Loop: LD 2 LD 3 LD 4 LD 5 ADDD 6 ADDD 7 ADDD 8 ADDD 9 SD 10 SD 11 SD 12 SUBI 13 BNEZ 14 SD F 0, 0(R 1) F 6, -8(R 1) F 10, -16(R 1) F 14, -24(R 1) F 4, F 0, F 2 F 8, F 6, F 2 F 12, F 10, F 2 F 16, F 14, F 2 0(R 1), F 4 -8(R 1), F 8 -16(R 1), F 12 R 1, #32 R 1, LOOP 8(R 1), F 16 • What assumptions made when moved code? – OK to move store past SUBI even though changes register – OK to move loads before stores: get right data? – When is it safe for compiler to do such changes? ; 8 -32 = -24 14 clock cycles, or 3. 5 per iteration When safe to move instructions? 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 30

Getting CPI < 1: Issuing Multiple Instructions/Cycle • Two main variations: Superscalar and VLIW • Superscalar: varying no. instructions/cycle (1 to 6) – Parallelism and dependencies determined/resolved by HW – IBM Power. PC 604, Sun Ultra. Sparc, DEC Alpha 21164, HP 7100 • Very Long Instruction Words (VLIW): fixed number of instructions (16) parallelism determined by compiler – Pipeline is exposed; compiler must schedule delays to get right result • Explicit Parallel Instruction Computer (EPIC)/ Intel – 128 bit packets containing 3 instructions (can execute sequentially) – Can link 128 bit packets together to allow more parallelism – Compiler determines parallelism, HW checks dependencies and fowards/stalls 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 31

Getting CPI < 1: Issuing Multiple Instructions/Cycle • Superscalar DLX: 2 instructions, 1 FP & 1 anything else – Fetch 64 bits/clock cycle; Int on left, FP on right – Can only issue 2 nd instruction if 1 st instruction issues – More ports for FP registers to do FP load & FP op in a pair Type Pipe Int. instruction FP instruction Int. instruction WB FP instruction WB Int. instruction MEM WB FP instruction 10/24/01 MEM WB Stages IF ID EX MEM WB IF ID EX MEM IF ID EX IF ID ©UCB Fall 2001 EX CS 152 / Kubiatowicz Lec 15. 32

Loop Unrolling in Superscalar Integer instruction Loop: FP instruction LD F 0, 0(R 1) 1 LD F 6, 8(R 1) 2 LD F 10, 16(R 1) ADDD F 4, F 0, F 2 3 LD F 14, 24(R 1) ADDD F 8, F 6, F 2 4 LD F 18, 32(R 1) ADDD F 12, F 10, F 2 SD 0(R 1), F 4 ADDD F 16, F 14, F 2 SD 8(R 1), F 8 ADDD F 20, F 18, F 2 SD 16(R 1), F 12 8 SD 24(R 1), F 16 9 SUBI R 1, #40 10 BNEZ R 1, LOOP 11 SD 32(R 1), F 20 12 Clock cycle 5 6 7 • Unrolled 5 times to avoid delays (+1 due to SS) • 12 clocks, or 2. 4 clocks per iteration 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 33

Limits of Superscalar • While Integer/FP split is simple for the HW, get CPI of 0. 5 only for programs with: – Exactly 50% FP operations – No hazards • If more instructions issue at same time, greater difficulty of decode and issue – Even 2 scalar => examine 2 opcodes, 6 register specifiers, & decide if 1 or 2 instructions can issue • VLIW: tradeoff instruction space for simple decoding – The long instruction word has room for many operations – By definition, all the operations the compiler puts in the long instruction word can execute in parallel – E. g. , 2 integer operations, 2 FP ops, 2 Memory refs, 1 branch » 16 to 24 bits per field => 7*16 or 112 bits to 7*24 or 168 bits wide – Need compiling technique that schedules across several branches 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 34

Loop Unrolling in VLIW Memory reference 1 Memory FP reference 2 LD F 0, 0(R 1) LD F 10, 16(R 1) LD F 18, 32(R 1) LD F 26, 48(R 1) LD F 6, 8(R 1) 1 LD F 14, 24(R 1) 2 LD F 22, 40(R 1) ADDD F 4, F 0, F 2 ADDD F 8, F 6, F 2 ADDD F 12, F 10, F 2 ADDD F 16, F 14, F 2 4 ADDD F 20, F 18, F 2 ADDD F 24, F 22, F 2 5 SD 8(R 1), F 8 ADDD F 28, F 26, F 2 SD 24(R 1), F 16 7 SD 40(R 1), F 24 SUBI R 1, #48 BNEZ R 1, LOOP 9 SD 0(R 1), F 4 SD 16(R 1), F 12 SD 32(R 1), F 20 SD 0(R 1), F 28 FP Int. op/ Clock operation 1 op. 2 branch 3 6 8 Unrolled 7 times to avoid delays 7 results in 9 clocks, or 1. 3 clocks per iteration Need more registers in VLIW(EPIC => 128 int + 128 FP) 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 35

Software Pipelining • Observation: if iterations from loops are independent, then can get more ILP by taking instructions from different iterations • Software pipelining: reorganizes loops so that each iteration is made from instructions chosen from different iterations of the original loop ( Tomasulo in SW) 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 36

Software Pipelining Example After: Software Pipelined 1 2 3 4 5 SD ADDD LD SUBI BNEZ • Symbolic Loop Unrolling 0(R 1), F 4 ; Stores M[i] F 4, F 0, F 2 ; Adds to M[i-1] F 0, -16(R 1); Loads M[i-2] R 1, #8 R 1, LOOP overlapped ops Before: Unrolled 3 times 1 LD F 0, 0(R 1) 2 ADDD F 4, F 0, F 2 3 SD 0(R 1), F 4 4 LD F 6, -8(R 1) 5 ADDD F 8, F 6, F 2 6 SD -8(R 1), F 8 7 LD F 10, -16(R 1) 8 ADDD F 12, F 10, F 2 9 SD -16(R 1), F 12 10 SUBI R 1, #24 11 BNEZ R 1, LOOP SW Pipeline Time Loop Unrolled – Maximize result use distance – Less code space than unrolling Time – Fill & drain pipe only once per loop vs. once per each unrolled iteration in loop unrolling 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 37

Software Pipelining with Loop Unrolling in VLIW Memory reference 1 Memory reference 2 FP operation 1 FP op. 2 Int. op/ branch Clock LD F 0, 48(R 1) ST 0(R 1), F 4 ADDD F 4, F 0, F 2 LD F 6, 56(R 1) ST 8(R 1), F 8 ADDD F 8, F 6, F 2 SUBI R 1, #24 2 LD F 10, 40(R 1) ST 8(R 1), F 12 ADDD F 12, F 10, F 2 BNEZ R 1, LOOP 3 1 • Software pipelined across 9 iterations of original loop – In each iteration of above loop, we: » Store to m, m 8, m 16 (iterations I 3, I 2, I 1) » Compute for m 24, m 32, m 40 (iterations I, I+1, I+2) » Load from m 48, m 56, m 64 (iterations I+3, I+4, I+5) • 9 results in 9 cycles, or 1 clock per iteration • Average: 3. 3 ops per clock, 66% efficiency Note: Need less registers for software pipelining (only using 7 registers here, was using 15) 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 38

Can we use HW to get CPI closer to 1? • Why in HW at run time? – Works when can’t know real dependence at compile time – Compiler simpler – Code for one machine runs well on another • Key idea: Allow instructions behind stall to proceed: DIVD ADDD SUBD F 0, F 2, F 4 F 10, F 8 F 12, F 8, F 14 • Out of order execution => out of order completion. • Disadvantages? – Complexity – Precise interrupts harder! (Talk about this next time) 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 39

Problems? • How do we prevent WAR and WAW hazards? • How do we deal with variable latency? – Forwarding for RAW hazards harder. RAW WAR 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 40

Summary • Precise interrupts are easy to implement in a 5 stage pipeline: – Mark exception on pipeline state rather than acting on it – Handle exceptions at one place in pipeline (memory stage/beginning of writeback) • Loop unrolling Multiple iterations of loop in software: – Amortizes loop overhead over several iterations – Gives more opportunity for scheduling around stalls • Software Pipelining take one instruction from each of several iterations of the loop – Software overlapping of loop iterations • Very Long Instruction Word machines (VLIW) Multiple operations coded in single, long instruction – Requires compiler to decide which ops can be done in parallel – Trace scheduling find common path and schedule code as if branches didn’t exist (+ add “fixup code”) 10/24/01 ©UCB Fall 2001 CS 152 / Kubiatowicz Lec 15. 41