CS 152 Computer Architecture and Engineering Lecture 2

CS 152 Computer Architecture and Engineering Lecture 2 - Simple Machine Implementations Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http: //www. eecs. berkeley. edu/~krste http: //inst. eecs. berkeley. edu/~cs 152 January 24, 2012 CS 152 Spring 2012

Last Time in Lecture 1 • Computer Architecture >> ISAs and RTL – CS 152 is about interaction of hardware and software, and design of appropriate abstraction layers • Comp. Arch. shaped by technology and applications – History provides lessons for the future • First 130 years of CA, from Babbage to IBM 360 – Move from calculators (no conditionals) to fully programmable machines – Rapid change started in WWII (mid-1940 s), move from electromechanical to pure electronic processors • Cost of software development becomes a large constraint on architecture (need compatibility) • IBM 360 introduces notion of “family of machines” running same ISA but very different implementations – Six different machines released on same day (April 7, 1964) – “Future-proofing” for subsequent generations of machine January 24, 2012 CS 152 Spring 2012 2

IBM 360: Initial Implementations Model 30. . . Storage 8 K - 64 KB Datapath 8 -bit Circuit Delay 30 nsec/level Local Store Main Store Control Store Read only 1 sec Model 70 256 K - 512 KB 64 -bit 5 nsec/level Transistor Registers Conventional circuits IBM 360 instruction set architecture (ISA) completely hid the underlying technological differences between various models. Milestone: The first true ISA designed as portable hardware-software interface! With minor modifications it still survives today! January 24, 2012 CS 152 Spring 2012 3

Instruction Set Architecture (ISA) • The contract between software and hardware • Typically described by giving all the programmervisible state (registers + memory) plus the semantics of the instructions that operate on that state • IBM 360 was first line of machines to separate ISA from implementation (aka. microarchitecture) • Many implementations possible for a given ISA – E. g. , the Soviets build code-compatible clones of the IBM 360, as did Amdahl after he left IBM. – E. g. 2. , today you can buy AMD or Intel processors that run the x 8664 ISA. – E. g. 3: many cellphones use the ARM ISA with implementations from many different companies including TI, Qualcomm, Samsung, Marvell, etc. January 24, 2012 CS 152 Spring 2012 4

ISA to Microarchitecture Mapping • ISA often designed with particular microarchitectural style in mind, e. g. , – Accumulator hardwired, unpipelined – CISC microcoded – RISC hardwired, pipelined – VLIW fixed-latency in-order parallel pipelines – JVM software interpretation • But can be implemented with any microarchitectural style – Intel Sandy Bridge: hardwired pipelined CISC (x 86) machine (with some microcode support) – Simics: Software-interpreted SPARC RISC machine – ARM Jazelle: A hardware JVM processor – This lecture: a microcoded RISC-V machine January 24, 2012 CS 152 Spring 2012 5

Today, Microprogramming • To show to build very small processors with complex ISAs • To help you understand where CISC* machines came from • Because still used in common machines (IBM 360, x 86, Power. PC) • As a gentle introduction into machine structures • To help understand how technology drove the move to RISC* * CISC/RISC names came much later than the style of machines they refer to. January 24, 2012 CS 152 Spring 2012 6

Microarchitecture: Implementation of an ISA status lines Controller control points Data path Structure: How components are connected. Static Behavior: How data moves between components Dynamic January 24, 2012 CS 152 Spring 2012 7

Microcontrol Unit Maurice Wilkes, 1954 op conditional code flip-flop First used in EDSAC-2, completed 1958 Next state address Matrix A Matrix B Embed the control logic state table in a memory array Decoder Memory Control lines to ALU, MUXs, Registers January 24, 2012 CS 152 Spring 2012 8

Microcoded Microarchitecture busy? zero? opcode holds fixed microcode instructions controller (ROM) Datapath Data holds user program written in macrocode instructions (e. g. , x 86, RISC-V, etc. ) January 24, 2012 Addr Memory (RAM) CS 152 Spring 2012 en. Mem. Wrt 9

RISC-V ISA • • New RISC design from UC Berkeley Realistic & complete ISA, but open & small Not over-architected for a certain implementation style Both 32 -bit and 64 -bit address space variants – RV 32 and RV 64 • • Designed for multiprocessing Efficient instruction encoding Easy to subset/extend for education/research Techreport with RISC-V spec available on class website • We’ll be using 32 -bit RISC-V this semester in lectures and labs, very similar to MIPS you saw in CS 61 C January 24, 2012 CS 152 Spring 2012 10

RV 32 Processor State Program counter (pc) 32 x 32 -bit integer registers (x 0 -x 31) • x 0 always contains a 0 32 floating-point (FP) registers (f 0 -f 31) • each can contain a single- or doubleprecision FP value (32 -bit or 64 -bit IEEE FP) FP status register (fsr), used for FP rounding mode & exception reporting January 24, 2012 CS 152 Spring 2012 11

RISC-V Instruction Encoding • Can support variable-length instructions. • Base instruction set (RV 32) always has fixed 32 -bit instructions lowest two bits = 112 • All branches and jumps have targets at 16 -bit granularity (even in base ISA where all instructions are fixed 32 bits) January 24, 2012 CS 152 Spring 2012 12

RISC-V Instruction Formats Destination Reg. Source 2 Source 1 January 24, 2012 Additional opcode bits/immediat e CS 152 Spring 2012 7 -bit opcode field (but low 2 bits =112) 13

R-Type/I-Type/R 4 -Type Formats Reg-Reg ALU operations Reg-Imm ALU operations 12 -bit signed immediate Load instructions, (rs 1 + immediate) addressing Only used for floating-point fused multiply-add January 24, 2012 CS 152 Spring 2012 Reg. Source 3 14

B-Type 12 -bit signed immediate split across two fields Branches, compare two registers, PC+immediate target (Branches do not have delay slot) Store instructions, (rs 1 + immediate) addressing, rs 2 data January 24, 2012 CS 152 Spring 2012 15

L-Type Writes 20 -bit immediate to top of destination register. Used to build large immediates. 12 -bit immediates are signed, so have to account for sign when building 32 -bit immediates in 2 -instruction sequence (LUI high-20 b, ADDI low-12 b) January 24, 2012 CS 152 Spring 2012 16

J-Type “J” Unconditional jump, PC+offset target “JAL” Jump and link, also writes PC+4 to x 1 Offset scaled by 1 -bit left shift – can jump to 16 -bit instruction boundary (Same for branches) January 24, 2012 CS 152 Spring 2012 17

Data Formats and Memory Addresses Data formats: 8 -b Bytes, 16 -b Half words, 32 -b words and 64 -b double words Some issues • Byte addressing Big Endian vs. Little Endian Most Significant Byte 0 3 1 2 2 1 Least Significant Byte 3 0 Byte Addresses • Word alignment Suppose the memory is organized in 32 -bit words. Can a word address begin only at 0, 4, 8, . . ? 0 January 24, 2012 1 2 3 CS 152 Spring 2012 4 5 6 7 18

A Bus-based Datapath for RISC-V bcompare? Opcode ld. IR Op. Sel ld. A 32(PC) 1(Link) rd rs 2 rs 1 ld. B 2 rd rs 2 rs 1 IR Imm. Sel 2 Imm Ext en. Imm busy 3 A ALU control 32 GPRs + PC. . . 32 -bit Reg en. ALU data Bus MA addr B ALU Reg. Sel ld. MA Reg. Wrt Memory Mem. Wrt en. Reg data en. Mem 32 Microinstruction: register to register transfer (17 control signals) MA B PC means Reg. Sel = PC; en. Reg=yes; ld. MA= yes Reg[rs 2] means Reg. Sel = rs 2; en. Reg=yes; ld. B = yes January 24, 2012 CS 152 Spring 2012 19

Memory Module addr busy RAM din we Write(1)/Read(0) Enable dout bus Assumption: Memory operates independently and is slow as compared to Reg-to-Reg transfers (multiple CPU clock cycles per access) January 24, 2012 CS 152 Spring 2012 20

Instruction Execution of a RISC-V instruction involves 1. 2. 3. 4. 5. January 24, 2012 instruction fetch decode and register fetch ALU operation memory operation (optional) write back to register file (optional) + the computation of the next instruction address CS 152 Spring 2012 21

Microprogram Fragments instr fetch: MA PC IR Memory PC A + 4 dispatch on OPcode ALU: A Reg[rs 1] B Reg[rs 2] Reg[rd] func(A, B) do instruction fetch ALUi: A Reg[rs 1] B Imm sign extension Reg[rd] Opcode(A, B) do instruction fetch January 24, 2012 CS 152 Spring 2012 can be treated as a macro 22

Microprogram Fragments (cont. ) LW: A Reg[rs 1] B Imm MA A + B Reg[rd] Memory do instruction fetch J: A PC-4 B IR PC Jump. Targ(A, B) do instruction fetch Jump. Targ(A, B) = {A + B[31: 7]<<1} beq: A Reg[rs 1] B Reg[rs 2] If A==B then go to bz-taken do instruction fetch bz-taken: A PC-4 B BImm << 1 PC A + B do instruction fetch January 24, 2012 CS 152 Spring 2012 BImm = IR[31: 27, 16: 10] 23

RISC-V Microcontroller: first attempt pure ROM implementation Opcode bcompare? Busy (memory) 6 PC (state) s addr ROM size ? = 2(opcode+status+s) words Word size ? = control+s bits How big is “s”? s Program ROM data next state Control Signals (17) January 24, 2012 CS 152 Spring 2012 24

Microprogram in the ROM worksheet State Op zero? busy Control points next-state fetch 0 fetch 1 fetch 2 fetch 3 * * * yes no * * MA PC. . IR Memory A PC PC A + 4 fetch 1 fetch 2 fetch 3 ? fetch 3 ALU * * PC A + 4 ALU 0 * * * A Reg[rs 1] ALU 1 B Reg[rs 2] ALU 2 Reg[rd] func(A, B) fetch 0 ALU 1 ALU 2 January 24, 2012 * * * CS 152 Spring 2012 25

Microprogram in the ROM State Op fetch 0 fetch 1 fetch 2 fetch 3 fetch 3 fetch 3. . . ALU 0 ALU 1 ALU 2 January 24, 2012 zero? busy Control points * * ALUi LW SW J JAL JR JALR beq * * * * yes no * * * * * MA PC. . IR Memory A PC PC A + 4 PC A + 4 PC A + 4 * * * * * A Reg[rs 1] ALU 1 B Reg[rs 2] ALU 2 Reg[rd] func(A, B) fetch 0 CS 152 Spring 2012 next-state fetch 1 fetch 2 fetch 3 ALU 0 ALUi 0 LW 0 SW 0 JAL 0 JR 0 JALR 0 beq 0 26

Microprogram in the ROM Cont. State Op brcomp? busy ALUi 0 ALUi 1 ALUi 2. . . J 0 J 1 J 2. . . beq 0 beq 1 beq 2 beq 3 beq 4 beq 5. . . January 24, 2012 Control points next-state * * * * * A Reg[rs 1] B Imm Reg[rd] Op(A, B) * * * * * A PC J 1 B IR J 2 PC Jump. Targ(A, B) fetch 0 * * * * * yes no * * * * * A Reg[rs 1] B Reg[rs 2] A PC. . A PC-4 B BImm PC A+B CS 152 Spring 2012 ALUi 1 ALUi 2 fetch 0 beq 1 beq 2 beq 3 fetch 0 beq 4 beq 5 fetch 0 27

Size of Control Store / w status & opcode PC addr size = 2(w+s) x (c + s) Control signals Control ROM / s next PC data / c RISC-V: w = 6+2 c = 17 s=? no. of steps per opcode = 4 to 6 + fetch-sequence no. of states (4 steps per op-group ) x op-groups + common sequences = 4 x 8 + 10 states = 42 states s = 6 Control ROM = 2(8+6) x 23 bits 48 Kbytes January 24, 2012 CS 152 Spring 2012 28

Reducing Control Store Size Control store has to be fast expensive • Reduce the ROM height (= address bits) – reduce inputs by extra external logic each input bit doubles the size of the control store – reduce states by grouping opcodes find common sequences of actions – condense input status bits combine all exceptions into one, i. e. , exception/no-exception • Reduce the ROM width – restrict the next-state encoding Next, Dispatch on opcode, Wait for memory, . . . – encode control signals (vertical microcode) January 24, 2012 CS 152 Spring 2012 29

CS 152 Administrivia • Lab 1/PS 1 out • Overview of lab in Friday’s Section, 9 AM, 71 Evans Hall • Lab 1 and PS 1 due start of class Thursday Feb. 9 – No extensions for Problem set. Zero credit afterwards. – Problem sets graded on 0, 1, 2 scale – Up to two free lab extensions per student, up till next class (Tuesday). Zero credit afterwards. • Solutions to PS 1 released same day • Section reviewing PS 1, following Friday Feb 10 • First Quiz, in class, Tue Feb 14, 2 -3: 30 PM – Closed book, no calculators, no computers, no cellphones • PS 2 and Lab 2 handed out after Quiz 1 January 24, 2012 CS 152 Spring 2012 30

Collaboration Policy • Can collaborate to understand problem sets, but must turn in own solution. Some problems repeated from earlier years - do not copy solutions. (Quiz problems will not be repeated…) • Each student must complete directed portion of the lab by themselves. OK to collaborate to understand how to run labs – Use Piazza! – Lab reports must be readable English summaries. Zero credit for handing in output log files from experiments. • Can work in group of up to 3 students for open-ended portion of each lab – OK to be in different group for each lab -just make sure to label participants’ names clearly on each turned-in lab section. January 24, 2012 CS 152 Spring 2012 31

CS 152 • We’ll be in this room 306 Soda for rest of semester • Should be able to accommodate all waitlist • I’m excused from Jury Service! January 24, 2012 CS 152 Spring 2012 32

risc-v Controller V 2 Opcode absolute ext op-group input encoding reduces ROM height PC (state) address Jump. Type = next | spin | fetch | dispatch | ftrue | ffalse +1 PCSrc jump logic zero busy Control ROM data Control Signals (17) January 24, 2012 PC+1 CS 152 Spring 2012 next-state encoding reduces ROM width 33

Jump Logic PCSrc = Case Jump. Types next PC+1 spin if (busy) then PC else PC+1 fetch absolute dispatch op-group ftrue if (bcompare) then absolute else PC+1 ffalse if (bcompare) then PC+1 else absolute January 24, 2012 CS 152 Spring 2012 34

Instruction Fetch & ALU: RISC-V-Controller-2 State Control points fetch 0 fetch 1 fetch 2 fetch 3. . . ALU 0 ALU 1 ALU 2 MA PC IR Memory A PC PC A + 4 next spin next dispatch A Reg[rs 1] B Reg[rs 2] Reg[rd] func(A, B) next fetch ALUi 0 ALUi 1 ALUi 2 A Reg[rs 1] B Imm Reg[rd] Op(A, B) next fetch January 24, 2012 CS 152 Spring 2012 next-state 35

Load & Store: RISC-V-Controller-2 State Control points next-state LW 0 LW 1 LW 2 LW 3 LW 4 A Reg[rs 1] B Imm MA A+B Reg[rd] Memory next spin fetch SW 0 SW 1 SW 2 SW 3 SW 4 A Reg[rs 1] B BImm MA A+B Memory Reg[rs 2] next spin fetch January 24, 2012 CS 152 Spring 2012 36

Branches: RISC-V-Controller-2 January 24, 2012 State Control points beq 0 beq 1 beq 2 beq 3 beq 4 A Reg[rs 1] B Reg[rs 2] A PC A A- 4 B BImm<<1 PC A+B CS 152 Spring 2012 next-state next ffalse next fetch 37

Jumps: RISC-V-Controller-2 State Control points J 0 J 1 J 2 A PC next B IR next PC Jump. Targ(A, B) fetch JR 0 JR 1 A Reg[rs 1] PC A JAL 0 JAL 1 JAL 2 JAL 3 JAL 4 A PC next Reg[1] A next A A-4 next B IR next PC Jump. Targ(A, B) fetch January 24, 2012 CS 152 Spring 2012 next-state next fetch 38

VAX 11 -780 Microcode January 24, 2012 CS 152 Spring 2012 39

Implementing Complex Instructions Opcode ld. IR bcompare? Op. Sel ld. A 32(PC) 1(Link) rd rs 2 rs 1 ld. B 2 IR Imm. Sel 2 Imm Ext en. Imm rd rs 2 rs 1 3 A ALU control Reg. Wrt 32 -bit Reg data Bus ld. MA MA addr 32 GPRs + PC. . . ALU Reg. Sel addr B en. ALU Memory Mem. Wrt en. Reg data en. Mem 32 rd M[(rs 1)] op (rs 2) M[(rd)] (rs 1) op (rs 2) M[(rd)] M[(rs 1)] op M[(rs 2)] January 24, 2012 busy CS 152 Spring 2012 Reg-Memory-src ALU op Reg-Memory-dst ALU op Mem-Mem ALU op 40

Mem-Mem ALU Instructions: RISC-V-Controller-2 Mem-Mem ALU op ALUMM 0 ALUMM 1 ALUMM 2 ALUMM 3 ALUMM 4 ALUMM 5 ALUMM 6 M[(rd)] M[(rs 1)] op M[(rs 2)] MA Reg[rs 1] A Memory MA Reg[rs 2] B Memory MA Reg[rd] Memory func(A, B) next spin fetch Complex instructions usually do not require datapath modifications in a microprogrammed implementation -- only extra space for the control program Implementing these instructions using a hardwired controller is difficult without datapath modifications January 24, 2012 CS 152 Spring 2012 41

Performance Issues Microprogrammed control multiple cycles per instruction Cycle time ? t. C > max(treg-reg, t. ALU, t ROM) Suppose 10 * t ROM < t. RAM Good performance, relative to a single-cycle hardwired implementation, can be achieved even with a CPI of 10 January 24, 2012 CS 152 Spring 2012 42

Horizontal vs Vertical m. Code Bits per Instruction # Instructions • Horizontal code has wider instructions – Multiple parallel operations per instruction – Fewer microcode steps per macroinstruction – Sparser encoding more bits • Vertical code has narrower instructions – Typically a single datapath operation per instruction – separate instruction for branches – More microcode steps per macroinstruction – More compact less bits • Nanocoding – Tries to combine best of horizontal and vertical code January 24, 2012 CS 152 Spring 2012 43

Nanocoding Exploits recurring control signal patterns in code, e. g. , ALU 0 A Reg[rs 1]. . . ALUi 0 A Reg[rs 1]. . . PC (state) code next-state address code ROM nanoaddress nanoinstruction ROM data • MC 68000 had 17 -bit code containing either 10 -bit jump or 9 -bit nanoinstruction pointer – Nanoinstructions were 68 bits wide, decoded to give 196 control signals January 24, 2012 CS 152 Spring 2012 44

Microprogramming in IBM 360 M 30 Datapath width (bits) inst width (bits) code size (K µinsts) store technology store cycle (ns) memory cycle (ns) Rental fee ($K/month) M 40 M 50 M 65 8 16 32 64 50 52 85 87 4 4 2. 75 CCROS TCROS BCROS 750 625 500 200 1500 2000 750 4 7 15 35 Only the fastest models (75 and 95) were hardwired January 24, 2012 CS 152 Spring 2012 45

IBM Card Capacitor Read-Only Storage Punched Card with metal film Fixed sensing plates [ IBM Journal, January 1961] January 24, 2012 CS 152 Spring 2012 46

Microcode Emulation • IBM initially miscalculated the importance of software compatibility with earlier models when introducing the 360 series • Honeywell stole some IBM 1401 customers by offering translation software (“Liberator”) for Honeywell H 200 series machine • IBM retaliated with optional additional microcode for 360 series that could emulate IBM 1401 ISA, later extended for IBM 7000 series – one popular program on 1401 was a 650 simulator, so some customers ran many 650 programs on emulated 1401 s – (650 simulated on 1401 emulated on 360) January 24, 2012 CS 152 Spring 2012 47

Microprogramming thrived in the Seventies • Significantly faster ROMs than DRAMs were available • For complex instruction sets, datapath and controller were cheaper and simpler • New instructions , e. g. , floating point, could be supported without datapath modifications • Fixing bugs in the controller was easier • ISA compatibility across various models could be achieved easily and cheaply Except for the cheapest and fastest machines, all computers were microprogrammed January 24, 2012 CS 152 Spring 2012 48

Writable Control Store (WCS) • Implement control store in RAM not ROM – MOS SRAM memories now almost as fast as control store (core memories/DRAMs were 2 -10 x slower) – Bug-free microprograms difficult to write • User-WCS provided as option on several minicomputers – Allowed users to change microcode for each processor • User-WCS failed – – – Little or no programming tools support Difficult to fit software into small space Microcode control tailored to original ISA, less useful for others Large WCS part of processor state - expensive context switches Protection difficult if user can change microcode Virtual memory required restartable microcode January 24, 2012 CS 152 Spring 2012 49

Modern Usage • Microprogramming is far from extinct • Played a crucial role in micros of the Eighties DEC u. VAX, Motorola 68 K series, Intel 286/386 • Microcode pays an assisting role in most modern micros (AMD Bulldozer, Intel Sandy Bridge, Intel Atom, IBM Power. PC) • Most instructions are executed directly, i. e. , with hard-wired control • Infrequently-used and/or complicated instructions invoke the microcode engine • Patchable microcode common for post-fabrication bug fixes, e. g. Intel processors load µcode patches at bootup January 24, 2012 CS 152 Spring 2012 50

Acknowledgements • These slides contain material developed and copyright by: – – – Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) • MIT material derived from course 6. 823 • UCB material derived from course CS 252 January 24, 2012 CS 152 Spring 2012 51