Chapter 4 RFID tag chip design Figure 4

Chapter 4 – RFID tag chip design

Figure 4. 1 Tag system architecture

Figure 4. 2 The “frame-sync” sequence of Gen 2 protocol

Figure 4. 3 Multi-level supply voltage generation

Figure 4. 4 An N-stage Dickson charge pump

Figure 4. 5 The factors affecting the power conversion efficiency of the charge pump

Figure 4. 6 Charge pump circuit with self-threshold compensation

Figure 4. 7 Charge pump circuit with constant threshold compensation and substrate shift

Figure 4. 8 Symmetrical charge pump circuit with dynamic threshold compensation

Figure 4. 9 Oscillator based TRNG

Figure 4. 10 Logical memory map （redrawn from ISO 18000 -6 C. ）

Figure 4. 11 Basic single-end SPNVM cell structure

Figure 4. 12 Schematic (a) control capacitor Mc and tunneling capacitor Mt (b) cross section

Figure 4. 13 General standard CMOS e. NVM architecture

Figure 4. 14 (a)Voltage-mode sense amplifier (b) Current-mode sense amplifier

Figure 4. 15 Block diagram of RFID tag baseband

Figure 4. 16 Decode Margin for 1. 28 MHz with 5% clock uncertainty (violations marked with the circle)

Figure 4. 17 Decode Margin for 1. 92 MHz with 5% clock uncertainty

Figure 4. 18 BLF error when clock rate is 1. 28 MHz (violations marked with the circle)

Figure 4. 19 BLF error when clock rate is 1. 92 MHz

Figure 4. 20 Clock Gating

Figure 4. 21 Example of adiabatic CMOS circuit (left) versus standard CMOS Logic (right)

Figure 4. 22 Energy dissipation in the adiabatic circuit

Figure 4. 23 The different package of on-chip antenna and tag chip