XC 9500 CPLDs Supporting the Total Product Life

XC 9500 CPLDs “Supporting the Total Product Life Cycle” 1 Technical seminar

Designer's Needs w In-System Programming w Enhanced Testability w Design changes without PCB changes w Mixed 5 V/3. 3 V I/Os w High endurance reprogramming w Multiple speeds/densities in identical pinouts and packages 2 Technical seminar

The Industry’s First 5 V Flash CPLD w 5 V In-System Programming (ISP) w High performance — 5 ns pin-to-pin speed — 125 MHz count frequency w Large density range — 36 to 288 macrocells (Phase 1 family) w Flexible architecture — optimized for pin-locking — global and product term clock, set/reset, OE w Most complete IEEE 1149. 1 (JTAG) w Highest reprogramming endurance 3 — 10, 000 program/erase Technical seminar cycles

Smaller Cell Size with Fast. FLASH Cell Typical E 2 CPLD Cell 1/3 Area w Product benefits due to smaller cell 4 More routing switches in the same area supports pinlocking 4 Lower parasitic capacitance improves performance 4 Long term cost improvements due to scalability 4 Technical seminar

XC 9500 Architectural Features w Predictable, all pins fast, PAL-like architecture w Fast. CONNECT switch matrix provides 100% routing with 100% device utilization w Flexible function block — 36 inputs with 18 outputs — product term expansion with up to 90 product terms per macrocell — global and product term clocks — global and product term 3 -state enables — global and product term set/reset signals 5 Technical seminar

XC 9500 Architecture 3 JTAG Port JTAG Controller In-System Programming Controller Function Block 1 I/O Function Block 2 I/O I/O - Global Clocks I/O - Global Set/Reset I/O - Global Tri-States Blocks Fast. CONNECT Switch Matrix Function Block 3 3 1 Function Block n 2 or 4 6 Technical seminar

Fast. FLASH Function Block Global Clocks 3 Macrocell 1 AND Array Global 3 -State 2 I/O Product. Term Allocator 36 From Fast. CONNECT Macrocell 18 To Fast. CONNECT 7 Technical seminar I/O

XC 9500 Macrocell to/from other macrocells From Fast. CONNECT SUM-Term Logic 36 P-Term Allocator XOR D/T to/from other macrocells Q R S P-term Clk P-term R&S P-term OE 3 8 Register Global Clocks Technical seminar 2 or 4 Global R/S OEs 18

XC 9500 Advanced Macrocell From Upper Macrocell To Upper Macrocell Global S/R Global CLKs Global S/R Product Term OE From Lower Macrocell 9 To Lower Macrocell Technical seminar

Flexible Cascading w Fast Forwards 3 p-terms, retains 2 p-terms w Bi-directional cascade Forwards 5 — collects/delivers available p-terms w Automatically controlled by software Delivers 5 p-terms w One p-term granularity level Delivers 5 p-terms 10 Technical seminar Macrocell Logic with 18 p-terms

Feedback Paths w Fast. CONNECT w Pin w Local Fast. CONNECT FB X Macrocell Local feedback Fast. CONNECT feedback Pin feedback 11 Technical seminar

Complete Interconnectivity with Fast. CONNECT™ Global S/R Global 3 -State Function Block Fast. CONNECT Function Block Global Clocks JTAG 12 Function Block Technical seminar

Restrictive Max 7000/S Interconnect 1 2 3 4 36 Pin Inputs (~ 2 entries / LAB) Macrocells (~2 entries / LAB) 13 Technical seminar

XC 9500 Fast. CONNECT 1 2 3 4 36 Pin Inputs (~ 3 entries / FB) 14 Macrocel ls (36 entries / FB) Technical seminar

What is Pin-Locking? w Ability to retain device pin assignments for small to medium design changes — — — introducing a new variable to existing terms adding input signals inverting signals introducing 1 or 2 buried flip flops adding p-terms w Requires a symmetric, uniform architecture w Requires software focus on pin-locking 15 Technical seminar

Pin-Locking is Key for ISP w Must retain pinouts as the design evolves — best done when the design software initially assigns pins — different from pinout pre-assigning — strong function of utilization in typical CPLD architectures — result of both architecture and software strategy w Pin-locking is valuable — eliminates or reduces PC Board rework — minimizes time to market, saves money — lowers designer frustration, risk 16 Technical seminar

Leading Edge Features Support Superior Pin Locking for ISP 3 X more routing switches - superior input/feedback routability Largest block fan-in Fast. CONNECT Function Block - 36 direct inputs - wired-AND provides extra logic/more fan-in I/O Block 36 Wired-AND Capability Function Block Powerful bi-directional logic allocation - any number of p-terms (up to 90 max. ) 17 Technical seminar

XC 9500 Supports Design Changes with Fixed Pinouts Design Change XC 9500 Feature è Add another input pin or FB output Fast. CONNECT switch matrix with 100% connectivity è Add more logic in XC 9500 allows expansion the macrocell up to 90 P-terms è Add additional input 36 total inputs are available connections to the FB plus Fast. CONNECT AND gate capability 18 Technical seminar

XC 9500 System Features w Enhanced Data Security Features — Read security bits prevent unauthorized reading — Write security bits prevent accidental program/erase w Reduced power option per macrocell w 3. 3 v/5 v outputs w 24 m. A, 100% PCI compliant Additional Ground Pin • Lower ground inductance • Reduce ground noise Internal Logic w Output Noise Reduction — Slew rate control — User programmable ground pin capability User Programmable Ground Pin User I/O Pin Ground Pin 19 Technical seminar

Advanced System Features w Enhanced Data Security Features — Read security bit prevents unauthorized reading — Write security bit prevents inadvertent user program/erase w System Power Reduction — Reduced power option per macrocell w Output drive capability — 3. 3 v/5 v outputs — 24 m. A, 100% PCI compliant outputs w Output Noise Reduction in High-Pincount PQFP Packages — Slew rate control — User programmable ground pins 20 Technical seminar

Planned Fast. FLASH™ CPLD Family Phase II Expansion 0. 6µ Phase I Family XC 9536 XC 9572 XC 95108 XC 95144 XC 95180 XC 95216 XC 95288 XC 95432 XC 95576 Macrocells 36 72 108 144 180 216 288 432 576 Usable Gates 800 1600 2400 3200 4000 4800 6400 9600 12800 t. PD (ns) 5 7. 5 10 10 10 12 15 Registers 36 72 108 144 180 216 288 432 576 34 72 108 133 168 192 240 84 PC 100 PQ 160 PQ 208 PQ 160 PQ 208 PQ 304 PQ Max. User I/Os Packages 21 44 PC 44 PQ Technical seminar

The Next Generation CPLD w The Industry’s first 5 V Flash CPLD w Highest program/erase reliability of 10, 000 cycles w The best Pin-Locking CPLD architecture w Most complete manufacturing and engineering JTAG support Support for the Total Product Life Cycle 22 Technical seminar