XC 9500 XL XC 9500 XL Overview w
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XC 9500 XL
XC 9500 XL Overview w Optimized for 3. 3 -V systems l 0. 35 micron Fast. FLASH technology 4 Layers of Metal compatible levels with 5. 0/2. 5 V Reprogramming Endurance = 10, 000 l Charge Retention = 20 years l l l w Meets performance requirements l high f. MAX = 200 MHz / fast t. PD = 4 ns w Best ISP/JTAG support in industry w Best pinlocking in industry w Advanced packaging - New CSPs !
XC 9500 XL Architecture New extra-wide function block inputs – Uniform – Identical Functional Blocks – Identical Macrocells – Identical I/O pins – 5 ns pin-to-pin – 36 to 288 Macrocells (6400 gates) – Abundant Global Product Term Resources – Hysteresis on all inputs – Pullup/Bus Hold Option on Pins at power on – Great synthesis results
Fast. CONNECT II Switch Matrix w Very High Speed Switch Matrix w 2 nd Generation switch matrix w Used Fast Flash technology w Greater connectability for all signals w High routability at high utilization w Software delivers high speed automatically w Substantial power reduction
XC 9500 XL Feedback Paths w Fast. CONNECT w Pin Fast. CONNECT w Local FB X Macrocell Local feedback Fast. CONNECT feedback Pin feedback
XC 9500 XL Function Block w Handles SDRAM address width with 54 inputs l highest function block fan-in on fast CPLDs
XC 9500 XL Macrocell Flexible clocking and three-state control Local macrocell clock inversion control
Product Term Allocator Cascading 3 available here 2 p-terms required here 5 available here 5 native p-terms 5 available here Total = 18 requires 2 cascade times added to t. PD
Voltage Compatibility VCCINT = 3. 3 V VCCIO = 3. 3 V/2. 5 V CORE LOGIC Note: output p-channel gives full rail swing
Voltage Compatibility 2. 5/3. 3/5 V 2. 5 V 5 V VCCINT 3. 3 V VCCIO Any 5 V TTL device 5 V VCCINT 3. 3 V XC 9500 XL Any 2. 5/3. 3 V device
XC 9500 XL Voltage Compatibility Summary EIA Standard Voltage Levels No Power Supply Sequencing Restriction 5 V CMOS 5 V TTL 3. 3 V LVCMOS 3. 3 V LVTTL 2. 5 V Normal VIL X X X VIH X X X VOL X X X VOH 3. 3 V X X X
Input Signal Hysteresis VOH 50 m. V VOUT (VOLTS) VOL 1. 40 V VIN (VOLTS) 1. 45 V
Power Optimization w 67% decrease from 5 V CPLDs w Low power option per macrocell w Even lower power if I/Os swing 0 -2. 5 V w Fast. CONNECT II lower power than XC 9500 w I/Os swing full VCCIO range with pchannel pullups (shuts off attached external logic)
ISP (In System Programming) w Original XC 9500 JTAG and ISP instructions w New instruction: CLAMP l permits pin by pin definition of logic level w Added S/W support with XACT M 1. 5 w Same third party and ATE support package as XC 9500 CPLDs (HP, Gen. RAD, Teradyne)
XC 9500 XL Fits In Industry Standard JTAG Chains TDI XC 9500 DSP u. P XC 9500 XC 4000 EX TMS TCK TDO ASIC
Third Party ATE Support w Hewlett-Packard w Teradyne w Gen-RAD w Common Support for both Xilinx FPGAs and CPLDs.
Advanced CSP Packaging Supports high-growth market segments: Communications, Computers, Consumer Uses standard IR techniques for mounting to PC board
What’s Key for Pin-Locking w Must retain pinouts as the design evolves l l best done when the design software initially assigns pins different from pinout pre-assigning strong function of utilization in typical CPLD architectures result of both architecture and software strategy w Pin-locking is valuable l l l eliminates or reduces PC Board rework minimizes time to market, saves money lowers designer frustration, risk
3 Keys to Pin-Locking ¶ Global S/R Fully Populated Switch Matrix Function Block Fast. CONNECT Function Block w 2 nd generation switch matrix: 4 Complete interconnect of all pins & blocks Function Block JTAG Global 3 -State Function Block Global Clocks 4 All pin-to-pin paths at full speed
3 Keys to Pin-Locking Macrocell Ì Flexible Logic Allocation Global Clocks Function Ë Wide Block Fan-in 54 From Fast. CONNECT To Fast. CONNECT 3 Macrocell 1 Product Term Allocator AND Array Global 3 -State 2 I/O • Macrocell 18 I/O
XC 9500 XL Supports Design Changes with Fixed Pinouts Design Change XC 9500 XL Feature è Add another input pin or FB output Fast. CONNECT switch matrix with 100% connectivity è Add more logic in XC 9500 allows expansion the macrocell up to 90 P-terms è Add additional input 54 total inputs are available connections to the FB plus Fast. CONNECT AND gate capability
Pin-Locking Compare Table Routability Xilinx XC 9500 XL Altera Max 7 KS Lattice 1 K/2 K/3 K AMD Mach 5 Excellent Good* Poor Good Function block fan-in 54 36 18/24 32 Bi-directional individual product term allocation Yes No No No Maximum pterms/Mcell 90 32 32 32 Fully populated switch Yes No Notes: * Decreases with density
XC 9500 XL Other Features w Enhanced Data Security Features l l Read security bits prevent unauthorized reading Write security bits prevent accidental program/erase Additional Ground Pin w Reduced power option per macrocell • Lower ground inductance w 3. 3 v/5 v outputs • Reduce ground noise Internal Logic w 24 m. A, 100% PCI compliant User Programmable Ground Pin User I/O Pin w Output Noise Reduction l l Slew rate control User programmable ground pin capability User I/O Pin Ground Pin
XC 9500 XLSystem Designer’s CPLD Xilinx Feature System Designer Benefit 54 -input Function Block Superior connectivity & performance CLAMP instruction Better control of board & system signals during ISP 2. 5 V/3. 3 V/5 V I/O Capability Easy multi-voltage interfacing Invertible Local & Global PTerm Clocks and OEs Max number of clock & OE options Input Hystersis +/-50 m. V Improves noise margin; better slow signal response Bus Hold Totally controlled board initialization Common ISP/JTAG Support for CPLDs/FPGAs One language supports all Xilinx products
Xilinx CPLD Solutions 5 ns COMPARISON Specification XC 9500 -5 XL* XC 9500 -5** Voltage 3. 3 V 5 V t. PD (pin-to-pin speed) 5 ns* 5 ns t. SU (set-up speed) 3. 7 ns 4 ns t. CO (clock-to-out speed) 3. 5 ns 4 ns 5 ns 178. 6 MHz 100 MHz t. OE (output enable speed) f. SYS (system speed) Icc (supply current - typ) * XC 9500 XL also available in 4 ns version ** New 5 V speed specifications (as of 9/98) 11 m. A (Low Power) 18 m. A (Hi Perf) 30 m. A (Low Power) 50 m. A (Hi Perf)
XC 9500 XL Family 9536 XL 9572 XL 95144 XL 95288 XL Macrocells 36 72 Usable Gates 800 1600 3200 4 5 5 196 178 44 PC 64 VQ 100 TQ t. PD (ns) f. MAX (MHz) Packages QFPs CSPs/BGA 48 CS 144 178 100 TQ 144 CS 288 6400 6 151 144 TQ 208 PQ 352 BG
CPLD Solution for PC 99 SDRAM Controller Example Spartan. XL Personal Computer Memory USB Fire. Wire USB, Fire. Wire interfaces Device Bay Processor XC 9500 XL SDRAM Controller USB interface/ Fire. Wire interface
Challenges Facing the Design Engineer Small package 3. 3 V/2. 5 Design time V HDL entry 100 MHz minimum speed Board layout before design is complete Cost control Multiple SDRAM protocols Minimal programming overhead Sufficient address width Three-state flexibility Clock Resources for future flexibility expansion
Address[23: 0] Clock Reset Write Data[15: 0] Address[11: 0] CPLD SDRAM Controller CS RAS CAS WE SDRAMs Microprocessor Memory Interface Block Diagram Complete SDRAM Controller in a single CPLD
SDRAM Interface Close-up Address[23: 0] ADDR[23: 12] ADDR[11: 0] Data[15: 0] Refresh Counter Clock Reset Write Address Decode Chip Mode Select Register State Machine CS RAS CAS WE
CPLD Design on the Web 1 3 2 Design in VHDL, Verilog, ABEL, etc. Submit design to Web. FITTER Evaluate results w No software to load no user resources needed l no license l w Web. FITTER software always current l no upgrade CDs w Runs fast on network (minutes)
Web. FITTER Intro Page
Web. FITTER Activity Report
Web. FITTER Report File
SDRAM Controller Implementation in XC 9500 XL w Results for XC 95144 XL w Utilization l 52% of capacity available for other logic w Speed l faster than required for 133 MHz clock w Lowest-cost solution w Compare to chip sets and other CPLDs
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