Oct 2004 doc IEEE 802 15 04 0586

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Project: IEEE P 802. 15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [IEEE 802. 15. 4 b High Rate Alt-PHY proposals - Further Performance Comparison] Date Submitted: [27 Oct, 2004] Source: [Francois Chin] Company: [Institute for Infocomm Research, Singapore] Address: [21 Heng Mui Keng Terrace, Singapore 119613] Voice: [65 -6874 -5687] FAX: [65 -6774 -4990] E-Mail: [chinfrancois@i 2 r. a-star. edu. sg] Re: [Response to the call for proposal of IEEE 802. 15. 4 b, Doc Number: 15 -04 -0239 -00 -004 b] Abstract: [This presentation compares all proposals for the IEEE 802. 15. 4 b PHY standard. ] Purpose: [Proposal to IEEE 802. 15. 4 b Task Group] Notice: This document has been prepared to assist the IEEE P 802. 15. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P 802. 15. Submission 1 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Background – Main contribution of current doc is to provide further simulation results based on 1000 channel realisation, for the PHY proposals using coherent detection – Previous comparison used 100 channel realisation, as in IEEE Doc 15 -04 -0507 -04 -004 b – Performance comparison herein done with • {0, 1, 2} cyclic chip extension • {1, 2, 3} RAKE fingers Submission 2 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Updates – Corrected 3 -RAKE multipath performance for all proposals (due to programme bug in previous version) – Included PSSS performance with Precoding – Stated Recommendation simulation results Submission 3 based on corrected Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Candidates for Multipath Performance Comparison (using Coherent Chip Despreading) Code Set C 8 E 16 F 31 G 16 Description 8 -chip for Coh. Chip Despreading Orthogonal 16 DSSS PSSS 16 -chip for Coh. Chip Despreading Proposer I 2 R Helicomm Dr. Wolf & Assoc. I 2 R Doc # 04 -507 04 -314 04 -121 04 -507(new) Sym-Chip mapping Cyclic & Odd Bit Inversion Orthogonal Multi-code Cyclic & Odd Bit Inversion Bit/sym 4 4 15 4 Chip/Sym 8+1 cyclic extension 16 31+1 cyclic extension 16 Bit/chip 0. 44 0. 25 ~0. 47 0. 25 Root Sequence 5 C N. A. 08 B 3 E 375 2 F 53 Coh. Chip Despreading (CCD) Yes Yes Differential Chip Despreading (DCD) No No Submission Source: 15 -04 -0507 -04 -004 b 4 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Comparison Methodology – Multipath robustness performance • Investigation done with – Zero, one and two Cyclic chip(s) extension – One, two & three RAKE fingers – Bandwidth efficiency (bps / Hz) – RF requirement – Memory requirement Submission 5 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Multipath Realisations 1000 Channel Realisations at each RMS Delay Spread Submission 6 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Multipath Realisations 1000 Channel Realisations at each RMS Delay Spread Submission 7 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Proposed Symbol-to-Chip Mapping (8 -chip Code Set C 8) Decimal Value Binary Symbol Chip Value 0 0000 0 1 1 1 0 0 (Root – 5 C) 1 1000 00101110 2 0100 00010111 3 1100 10001011 4 0010 11000101 5 1010 11100010 6 0110 01110001 7 1110 10111000 8 0001 00001001 9 1001 10000100 10 0101 01000010 11 1101 00100001 12 0011 10010000 13 1011 01001000 14 0111 00100100 15 1111 00010010 The sequences are related to each other through cyclic shifts and/or conjugation (i. e. , inversion of odd-indexed chip values) Submission 8 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Other Root Sequences (8 -chip C 8 for Coherent Despreading only) • The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10: 9 18 23 29 33 36 46 58 66 71 72 92 111 113 116 123 132 139 142 144 163 184 189 197 209 219 222 226 232 237 246 Submission 9 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b DSSS Sequence E 16 Decimal Symbol Binary Symbol Chip Values 0 0000 001101000100 1 1000 011000010001 2 0100 000001110111 3 1100 010100100010 4 0010 0011101101001011 5 1010 0110111000011110 6 1110 00001111000 7 0111 0101110100101101 8 0001 001101001011 9 1001 011000011110 10 0101 000001111000 11 1101 010100101101 12 001110110100 13 1011 011011100001 14 0111 000010000111 15 1111 010111010010 Source doc. : IEEE 802. 15 -04 -0314 -02 -004 b Submission 10 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b PSSS Sequence F 31 (15 bit/32 chip) Source doc. : IEEE 802. 15 -04 -0121 -04 -004 b Submission 11 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Proposed Symbol-to-Chip Mapping (16 -chip Code Set G 16) Decimal Value Binary Symbol Chip Value 0 0000 0 0 1 1 1 1 0 1 0 0 1 1 (Root - 2 F 53) 1 1000 1100101111010100 2 0100 0011001011110101 3 1100 010010111101 4 0010 010100101111 5 1010 110101001011 6 0110 111101010010 7 1110 1011110101001100 8 0001 0111101000000110 9 1001111010000001 10 0101 0110011110100000 11 1101 000111101000 12 0011 000001111010 13 1011 100000011110 14 0111 101000000111 15 1111 1110100000011001 The sequences are related to each other through cyclic shifts and/or conjugation (i. e. , inversion of odd-indexed chip values) 12 Submission Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Other Root Sequences (8 -chip G 16 for Coherent Despreading only) • The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10: 1915 22715 44497 Submission 3566 31238 53420 12115 34297 61969 13 21038 42820 63620 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Multipath Performance (COBI 16 -chip) For 16 -chip COBI Sequence, No cyclic chip is needed when 3 RAKE is used. Submission 14 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Multipath Performance (COBI 8 -chip) For 8 -chip COBI Sequence, 1 Chip Extension is needed even with 3 -RAKE, due to weaker despreading strength (shorter code length). Submission 15 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Multipath Performance (DSSS) For DSSS, No cyclic chip is needed when 3 RAKE is used. Submission 16 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Multipath Performance (PSSS) For PSSS, best performance with 2 RAKE fingers + 1 chip extension. Precoding (according to 15 -04 -0121 -04 -004 b) & 3 rd RAKE do not seem to help. Submission 17 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b What happened to PSSS? Neighbouring parallel sequence is using M-Seq with 2 cyclic shifts in PSSS parallel sequence construction Source doc. : IEEE 802. 15 -04 -0121 -04004 b While other schemes enjoy better multipath performance with more RAKE fingers, PSSS can only use up to 2 fingers as the 3 rd RAKE is dominated by adjacent parallel bit sequence. PSSS is inter-parallel sequence interference limited Submission 18 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Coherent Receiver Multipath Performance • 1 chip extension is NOT necessary for 16 -chip sequence (COBI-16 & DSSS) if sufficient RAKE is used, even in dense multipath environment • 1 chip extension is necessary for 8 -chip COBI sequence, due to weaker despreading strength • General performance comparison: COBI sequence (16 chip) > COBI sequence (8+1 chip) > PSSS (31+1 chip, no Precoding) > DSSS Sequence (16 chip) Submission 19 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Coherent Receiver Multipath Performance What leads to Multipath robustness? Frequency selectivity leads to Inter-chip interference, and that is the killer…. To overcome, code must have good autocorrelation properties, i. e. low sidelodes Submission 20 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b How these codes achieve Multipath robustness? • COBI, maintain constant module, can at best achieve zero autocorrelation within 2 chips from cor. Peak; that is good enough to handle ICI of upto 2 chip periods • DSSS, comprising Walsh sequences, is not designed with auto-correlation sidelodes in mind COBI 8 -chip autocorrelation matrix • PSSS, uses flexibility in amplitude to achieve low (zero? ) autocorrelation throughout for each parallel sequence. However, it is inter-parallel sequence interference limited Submission 21 Francois Chin, Institute for Infocomm Research (I 2 R) COBI 16 -chip autocorrelation matrix

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Multipath Performance Summary (Coherent Chip Despreading) • To combat inter-chip interference due to relatively large channel delay spread (RMS delay spread / chip period ~ 0. 6, that is 2 us for 868 MHz band 0. 6 us for 915 MHz bands), 2 recommendations are: • RAKE combining (with 3 fingers) for all proposed sequences in receiver to combine path diversity; (this does not affect standard) • One additional chip extension to shorter code e. g. COBI 8 -chip sequence to avoid inter-symbol interference • With the 2 recommendations, under large channel delay spread • @ BER = 10 -5 (PER ~ 1% @ 127 byte-packet), 16 -chip COBI sequence have clear performance superiority (> 4 d. B better than the rest), followed by COBI (8+1 chip). Submission 22 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Candidates for Multipath Performance Comparison (using Coherent Chip Despreading) Code Set C 8 E 16 F 31 G 16 Description 8 -chip for Coh. Chip Despreading Orthogonal 16 DSSS PSSS 16 -chip for Coh. Chip Despreading Proposer I 2 R Helicomm Dr. Wolf & Assoc. I 2 R Doc # 04 -507 (new) 04 -314 04 -121 04 -507 (new) Sym-Chip mapping Cyclic & Odd Bit Inversion Orthogonal Multi-code Cyclic & Odd Bit Inversion Bit/sym 4 4 15 4 Chip/Sym 8+1 cyclic extension 16 31+1 cyclic extension 16 Bit/chip 0. 44 0. 25 ~0. 47 0. 25 Multipath performance Better Good Best Memory requirement Low Single sequence High 16 sequence Low Single sequence RF linearity requirement Low Moderate ~ high Low Note : Red - desirable Submission 23 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Coherent Detection Performance (at less channel delay spread) performance comparison: • Using 2 RAKE + 1 cyclic chip extension, COBI sequence (16 chip) > DSSS Sequence (16 chip) > COBI sequence (8+1 chip) > PSSS (31+1 chip) Again, PSSS can only use up to 2 fingers as the 3 rd RAKE is dominated by adjacent parallel bit sequence. PSSS is interparallel sequence interference limited. Precoding does give slightly better performance under less channel delay spread Submission 24 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Can Non-Coherent Detection be used? The COBI are designed to give best performance with coherent detection receiver. When the receiver employs non -coherent detection: • Yes, COBI sequence (16 chip) can handle multipath channels upto RMS delay spread / chip period ~ 0. 15 (that is 0. 5 us for 868 MHz band using 300 kcps and 0. 15 us for 915 MHz bands using 1 Mcps), which normally corresponds to short range indoor environment • Yes, COBI sequence (8+1 chip) can handle multipath channels upto RMS delay spread / chip period ~ 0. 03 (that is 0. 1 us for 868 MHz band using 300 kcps and 0. 03 us for 915 MHz bands using 1 Mcps), at even shorter range indoor Submission 25 Francois Chin, Institute for Infocomm Research (I 2 R)

Oct 2004 doc. : IEEE 802. 15 -04 -0586 -03 -004 b Code Sequence Recommendations • Multipath robustness vs complexity • As multipath robustness is vital, and differential chip despreading does not perform well under channels with excessive delay spread, coherent chip despreading with RAKE combining is necessary to ensure coverage in large indoor environment, e. g. industry space • One cyclic chip extension is ONLY necessary for shorter code, e. g. 8 -chip COBI, to avoid inter-symbol interference under channels with excessive delay spread • 8 -chip (+1 chip extension) & 16 -chip COBI sequence is recommended for its better multipathh performance, low RF linearity requirement, high bandwidth efficiency and low memory requirement • Differential chip despreading can also be used in shorter range indoor environment, e. g. residential space, where multipath channel RMS delay spread is small Submission 26 Francois Chin, Institute for Infocomm Research (I 2 R)