HDLBased Layout Synthesis Methodologies Allen C H Wu

HDL-Based Layout Synthesis Methodologies Allen C. -H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R. O. C {Email: chunghaw@cs. nthu. edu. tw}

Outline l Introduction l Timing analysis l Design planning l RTL timing budgeting l A timing-driven soft-macro placement and resynthesis method l Discussion

Why Needs HDL-based Design Methodologies? Design complexity Then Schematic capture Component mapping & may be some logic optimization Now HDL design specification Synthesis Place & route Layouts SW : assembly language => high-level language

An HDL-based Design Flow HDL design specification HDL coding Applications styles RTL synthesis Logic synthesis Layout architectures Layout synthesis Layouts Cell libraries

Top-Down Design Methodology HDL design specification RTL synthesis Logic synthesis Layouts Preserving design hierarchy Bridging the gap between RTL, logic, and layout synthesis

Applications and Layout Architectures l Datapath dominated designs : DSPs and processors. l Control dominated designs: controllers and communication chips. l Mixed type of designs. l Bit-sliced stacks. l Standard cells. l Macro-cell-based. l FPGAs.

Layout-driven Design methodology HDL design specification RTL synthesis Multi-level estimation engine Logic synthesis Layouts Back annotation

Design Estimation l Timing l Area l Power l Statistic VS. quick-synthesis methods l Analytical VS. constructive methods

Outline l Introduction l =>Timing analysis l Design planning l RTL timing budgeting l A timing-driven soft-macro placement and resynthesis method l Summary

Minimum Cycle Time Critical path Clock skew delay

Timing Analysis l Critical path delay analysis l Clock skew analysis l Timing analysis at different design levels l Delay calculation l Parasitic extraction l Accuracy VS. fidelity

Timing Analysis HDL design spec. HDL specification Logic synthesis Layouts Accuracy Complexity RTL synthesis Logic equations Cell-based netlists (Tech. dependent or independent) Floorplanning and P & R

RTL and Logic-level Timing Analysis HDL Spec. Macro Outputs Inputs Macro based Logic equations Cell-based netlist Unit and zero delay models for cells and wires

RTL Timing Analysis A Aspect ratio T Macro Floorplanning 1 2 A HDL design spec. Macro T Re-synthesis & re-floorplanning Back annotation 3 4 Aspect ratio 1 3 2 4

Chip-level Timing Analysis Macro cells Floorplanning Layout extraction Wiring delay l Taken into account inter-macro wiring delays. l Chip-level path enumeration. l Estimation vs. back annotation.

Macro-level Timing Analysis Netlists P&R Layout extraction Wiring delay information l Taken into account intra-macro wiring delays. l Path delay enumeration. l Estimation vs. back annotation.

Accuracy of Timing Analysis Design Stages Accuracy RTL 100+/-50%? ? ? Floorplanning 100+/-25% Placement 100+/-15% Global routing 100+/-7% Detailed routing 100+/-0% Source: DAC’ 97 Tutorial by Blaauw_Cong_Tsay

Outline l Introduction l Timing analysis l => Design planning l RTL timing budgeting l A timing-driven soft-macro placement and resynthesis method l Summary

Design Planning l Macro definitions l Soft macro generation l Macro placement l Pin assignment

Chip Planning I Soft macros Hard macros

Chip Planning II Soft macros Hard macros

Design Planning Considerations l How much timing, area, and power budgets should be assigned to each macro? l How to generate soft macros? - top-down - bottom-up l How to layout clock and power/ground network?

Design Budgeting Driving resistance Arrival time Macro Load capacitance Required arrival time RTL Spec. RTL & Logic synthesis Netlists Delay, area, power constraints ? ? ? ?

Soft Macro Generation Design Partitioning SM SM SM Clustering Based on design hierarchical information

Soft Macro Generation (Cont. ) Perform clustering techniques on a flattened netlist Clustering criteria: . Timing. Interconnect

Design Hierarchy Preservation Verilog design spec. HDL synthesis Macro formation Macro placement Macro to cell placement Initial placement HDLs Mod 1 Mod 2 Mod 3

Clock Network Styles l Mesh: robust, large area and power l Trunk: simple l Tree: min area, many supporting design algorithms

Clock Issues at RTL Critical path is determined from clock skew and skew cannot be determined until placement is completed! How to incorporate clock skew issues into early design planning? ? Still an open problem!

RTL Timing Analysis A Aspect ratio T Macro Floorplanning 1 2 A HDL design spec. Macro T Re-synthesis & re-floorplanning Back annotation 3 4 Aspect ratio 1 3 2 4

Timing-critical Macro Detection HDL spec. HDL synthesis Floorplanning Back annotation HDL Spec. Macro Critical macro Chip-level timing analysis

RTL Design Planning Macro Delay & area estimations Constructive or analytical method Back-annotation Floorplanning HDL Spec. Macro Cell library Back-annotation RTL timing analysis

Outline l Introduction l Timing analysis l Design planning l => RTL timing budgeting l A timing-driven soft-macro placement and resynthesis method l Summary

RTL Design Budgeting RTL Spec. Loop RTL/logic Synthesis Loop Netlists Physical-level Synthesis RTL sign-off Area Delay Power Budget? Loop HM SM 1 SM 2 SM 3 Chip Layout HM

Timing Budgeting Cross-macro timing paths!!! 1 Cycle

Timing Budgeting Issues l How to estimate delay and area from RTL specification? ? ? l After floorplanning? After RTL/logic synthesis? After placement? After routing? l Run time VS. accuracy? l How to distribute timing budget among macros? l No much work has been done in this area!!!

Timing Budgeting for Design Optimization A A x M 1 T A x M 2 T x T M 3 Minimize total area subject to satisfying the timing constraints.

Outline l Introduction l Timing analysis l Design planning l RTL timing budgeting l => A timing-driven soft-macro placement and resynthesis method l Summary

A Typical Design Flow for Macro-based Design HDL Description Back-annotation HDL Synthesis Timing Analysis Floorplanning P&R No OK? Yes Chip Layout

Design Hierarchy Preservation Preserving HDL design hierarchy for soft-macro placement? HDL Description M 1 M_12 M 2 HM HM SM HM A complete chip design methodology?

Considerations l How to utilize HDL design-hierarchy information to guide soft-macro placement procedure? l How to integrate design tasks and point tools at different design level to form a complete chip design methodology? l How to exploit the interaction between different design tasks.

Design Flow for Design Hierarchy Preservation HDL Description Floorplanning & Area Extraction HDL Synthesis SM Placement Pre-layout Timing Analysis P&R Back-annotation Structural-tree Construction SM Formation Post-layout Timing Analysis Chip Layout

Structural-tree Construction l The main objective is to preserve the design structural information from an HDL design description for macro formation. Top SM 4, 5 SM 1, 2 HM 1 SM 2 HM 2 SM 3 SM 4 SM 5

Soft macro Formation l Decomposition of large soft macros. - A large macro is too rigid for macro placement. l Clustering of small soft macros. - Many small macros increase the computational complexity.

Soft Macro Placement l Inputs: a set of software macros and the available area for soft macros. l Outputs: the relative location of each soft macro on the layout plane. l 1 st step: force-directed-based placement. l 2 nd step: Sweeping-based soft-macro assignment.

Floorplanning and Soft-Macro Area Extraction HM HM SM HM

Force-directed-based Placement HM SM 4 HM SM 2 SM 3 SM 1 HM HM

Soft-macro Placement Y SM 1 X SM 2 SM 3 SM 1 SM 2 SM 4 SM 3

The Experimental procedure: Design Synthesis HDL Description Synopsys (Design Compiler) Structural-tree Construction SM Formation Netlist

The Experimental Procedure: Floorplanning and P&R Netlist Cadence (Silicon Ensemble) SM Placement Cadence (HLDS) Cadence (Silicon Ensemble) Chip Layout

The Experimental Procedure: Timing Analysis Chip Layout Cadence (Hyper. Extract) AVANT! (STAR-DC) Synopsys (Design Time) Timing

Benchmarking Designs

Results

The Most Critical Path without Preserving Design Hierarchy

The Most Critical Path with Preserving Design Hierarchy

Resynthesis for Area/Delay Minimization Resynthesis for area minimization HM SM 1 SM 2 SM 3 HM Resynthesis for delay minimization HM SM 1 SM 2 SM 3 HM

Resynthesis-based Design Flow HDL Description P&R HDL Synthesis Timing Analysis Yes Floorplanning OK? SM Placement No Resynthesis Chip Layout

Slack Computation for Resynthesis Selection p 1 FF p 2 p 3 Macro POS(SM_i) = Slack(p_j), for all Slack(p_j) > 0. NEG(SM_i) = Slack(p_j), for all Slack(p_j) < 0.

The Experimental Design Flow HDL Description HDL Synthesis Synopsys (Design Compiler) Soft-macro Formation Block placement Cadence (Silicon Ensemble) Soft-macro placement P & R AVANT! (Aquarious XO) RC extraction AVANT! (STAR-RC) Delay calculation AVANT! (STAR-RC) Timing analysis Synopsys (Design Time) OK? yes no Resynthesis Synopsys (Design Compiler) Chip Layout

Benchmarking Designs

Results (Ind 2 using 0. 5 um tech. )

Results (Ind 2 using 0. 25 um tech. )

Results (Ave. Gate Delay VS. Interconnect Delay of Ind 2)

The Initial Critical Path of Ind 2 using the 0. 5 um Library

The Critical Path of Ind 2 after 2 Resynthesis Iterations

Discussion l How to perform timing analysis at different design stages? l Timing, area and power budgeting methods for early design planning? l Performance-driven and power-driven chip design methodologies.