Graphics Alexandra Nolte Gesine Marwedel 2003 Evaluation and

Graphics: © Alexandra Nolte, Gesine Marwedel, 2003 Evaluation and Validation Peter Marwedel TU Dortmund, Informatik 12 Germany 2011年 06 月 19 日 These slides use Microsoft clip arts. Microsoft copyright restrictions apply.

Application Knowledge Structure of this course 2: Specification 3: ES-hardware 4: system software (RTOS, middleware, …) Design repository 6: Application mapping Design 8: Test 7: Optimization 5: Evaluation & Validation (energy, cost, performance, …) Numbers denote sequence of chapters p. marwedel, informatik 12, 2011 - 2 -

Real-time calculus (RTC)/ Modular performance analysis (MPA) Thiele et al. (ETHZ): Extended network calculus: Arrival curves describe the maximum and minimum number of events arriving in some time interval . Examples: periodic event stream with jitter p-J p p p-J 3 3 2 2 1 1 p 2 p 3 p 2 p p p-J 3 p p+J p. marwedel, informatik 12, 2011 - 3 -

RTC/MPA: Service curves u resp. ℓ describe the maximum and minimum service capacity available in some time interval Example: TDMA bus bandwidth b s p s p-s p p. marwedel, informatik 12, 2011 p+s 2 p - 4 -

RTC/MPA: Workload characterization u resp. ℓ describe the maximum and minimum service capacity required as a function of the number e of events. Example: 16 u 12 WCET=4 l (Defined only for an integer number of events) 8 BCET=3 4 1 2 3 p. marwedel, informatik 12, 2011 e - 5 -

RTC/MPA: Workload required for incoming stream Incoming workload Upper and lower bounds on the number of events p. marwedel, informatik 12, 2011 - 6 -

RTC/MPA: System of real time components Incoming event streams and available capacity are transformed by real-time components: RTC’ RTC” … Theoretical results allow the computation of properties of outgoing streams p. marwedel, informatik 12, 2011 - 7 -

RTC/MPA: Transformation of arrival and service curves Resulting arrival curves: Remaining service curves: Where: p. marwedel, informatik 12, 2011 - 8 -

RTC/MPA: Remarks § Details of the proofs can be found in relevant references § Results also include bounds on buffer sizes and on maximum latency. § Theory has been extended into various directions, e. g. for computing remaining battery capacities p. marwedel, informatik 12, 2011 - 9 -

Application: In-Car Navigation System Car radio with navigation system User interface needs to be responsive Traffic messages (TMC) must be processed in a timely way Several applications may execute concurrently © Thiele, ETHZ p. marwedel, informatik 12, 2011 - 10 -

System Overview MMI Communication NAV RAD DB p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 11 -

Use case 1: Change Audio Volume < 200 ms MMI 0 m <5 s Communication NAV RAD DB p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 12 -

Use case 1: Change Audio Volume Communication Resource Demand p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 13 -

Use case 2: Lookup Destination Address < 200 ms MMI Communication NAV RAD DB p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 14 -

Use case 2: Lookup Destination Address p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 15 -

Use case 3: Receive TMC Messages MMI <1 000 ms Communication NAV RAD DB p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 16 -

Use case 3: Receive TMC Messages p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 17 -

Proposed Architecture Alternatives 22 MIPS 72 kbps MMI (A) 113 MIPS NAV 72 kbps 11 MIPS 113 MIPS 11 MIPS RAD NAV (E) 22 MIPS 113 MIPS MMI NAV 72 kbps 260 MIPS 57 kbps MMI (B) (D) 72 kbps (C) 22 MIPS 130 MIPS 260 MIPS RAD MMI RAD NAV p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 18 -

Step 1: Environment (Event Steams) Event Stream Model e. g. Address Lookup (1 event / sec) au [events] aℓ 1 1 p. marwedel, informatik 12, 2011 © Thiele, ETHZ [s] - 19 -

Step 2: Architectural Elements Event Stream Model e. g. Address Lookup (1 event / sec) au [events] al 1 Resource Model e. g. unloaded RISC CPU (113 MIPS) 1 [MIPS] [s] bl=bu 113 1 p. marwedel, informatik 12, 2011 © Thiele, ETHZ [s] - 20 -

Step 3: Mapping / Scheduling Rate Monotonic Scheduling (Pre-emptive fixed priority scheduling): § Priority 1: Change Volume (p=1/32 s) § Priority 2: Address Lookup (p=1 s) § Priority 3: Receive TMC (p=6 s) p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 21 -

Step 4: Performance Model CPU 1 a Change Volume b BUS MMI b CPU 3 CPU 2 b NAV b RAD a Address Lookup a Receive TMC MMI NAV RAD p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 22 -

Step 5: Analysis CPU 1 a Change Volume b BUS MMI b CPU 3 CPU 2 b NAV b RAD a Address Lookup a Receive TMC MMI NAV RAD p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 23 -

Analysis – Design Question 1 How do the proposed system architectures compare in respect to end-to-end delays? p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 24 -

Analysis – Design Question 1 End-to-end delays: (A) (B) p. marwedel, informatik 12, 2011 (C) (D) © Thiele, ETHZ (E) - 25 -

Analysis – Design Question 2 How robust is architecture A? Where is the bottleneck of this architecture? 22 MIPS MMI (A) 113 MIPS NAV 11 MIPS 72 kbps RAD p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 26 -

Analysis – Design Question 2 TMC delay vs. MMI processor speed: 26. 4 MIPS 22 MIPS MMI (A) 113 MIPS NAV p. marwedel, informatik 12, 2011 11 MIPS 72 kbps RAD © Thiele, ETHZ - 27 -

Conclusions § Easy to construct models (~ half day) § Evaluation speed is fast and linear to model complexity (~ 1 s per evaluation) § Needs little information to construct early models (Fits early design cycle very well) § Even though involved mathematics is very complex, the method is easy to use (Language of engineers) p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 28 -

Evaluation of designs according to multiple objectives Different design objectives/criteria are relevant: § Average performance § Worst case performance § Energy/power consumption § Thermal behavior § Reliability § Electromagnetic compatibility § Numeric precision § Testability § Cost § Weight, robustness, usability, extendibility, security, safety, environmental friendliness p. marwedel, informatik 12, 2011 - 29 -

Energy- and power models Power/energy models becoming increasingly important § due to mobile computing, § since energy availability becomes more relevant due to increased performance, and § due to environmental issues. p. marwedel, informatik 12, 2011 - 30 -

Energy models § Tiwari (1994): Energy consumption within processors § Simunic (1999): Using values from data sheets. Allows modeling of all components, but not very precise. § Russell, Jacome (1998): Measurements for 2 fixed configurations § Steinke et al. , Uni. Do (2001): mixed model using measurements and prediction § CACTI [Jouppi, 1996]: Predicted energy consumption of caches § Wattch [Brooks, 2000]: Power estimation at the architectural level, without circuit or layout p. marwedel, informatik 12, 2011 - 31 -

Steinke’s & Knauer’s model E. g. : ATMEL board with ARM 7 TDMI and ext. SRAM VDD m. A ARM 7 DAddr Register File Reg Value Barrel Shifter Etotal = Ecpu_instr + Ecpu_data + Emem_instr + Emem_data Reg# Imm Opcode Multiplier Data Memory IAddr Instr ALU Data Instruction Memory Instr. Decoder & Control Logic p. marwedel, informatik 12, 2011 - 32 -

Example: Instruction dependent costs in the CPU Cost for a sequence of m instructions Ecpu_instr = Min. Cost. CPU(Opcodei) + FUCost(Instri-1, Instri) 1 * w(Immi, j) + ß 1 * h(Immi-1, j, Immi, j) + 2 * w(Regi, k) + ß 2 * h(Regi-1, k, Regi, k) + 3 * w(Reg. Vali, k) + ß 3 * h(Reg. Vali-1, k, Reg. Vali, k) + 4 * w(IAddri) + ß 4 * h(IAddri-1, IAddri) w: number of ones; h: Hamming distance; FUCost: cost of switching functional units , ß: determined through experiments p. marwedel, informatik 12, 2011 - 33 -

Hamming Distance between adjacent addresses is playing major role p. marwedel, informatik 12, 2011 - 34 -

Results § It is not important, which address bit is set to ‘ 1‘ § The number of ‘ 1‘s in the address bus is irrelevant § The cost of flipping a bit on the address bus is independent of the bit position. § It is not important, which data bit is set to ‘ 1‘ § The number of ‘ 1‘s on the data bus has a minor effect (3%) § The cost of flipping a bit on the data bus is independent of the bit position. p. marwedel, informatik 12, 2011 - 35 -

CACTI model Comparison with SPICE Cache model used http: //research. compaq. com/wrl/people/jouppi/CACTI. html p. marwedel, informatik 12, 2011 - 36 -

Access times and energy consumption increase with the size of the memory Example (CACTI Model): "Currently, the size of some applications is doubling every 10 months" [STMicroelectronics, Medea+ Workshop, Stuttgart, Nov. 2003] p. marwedel, informatik 12, 2011 - 37 -

Influence of the associativity Parameters different from previous slides [P. Marwedel et al. , ASPDAC, 2004] p. marwedel, informatik 12, 2011 - 38 -

Evaluation of designs according to multiple objectives Different design objectives/criteria are relevant: § Average performance § Worst case performance § Energy/power consumption § Thermal behavior § Reliability § Electromagnetic compatibility § Numeric precision § Testability § Cost § Weight, robustness, usability, extendibility, security, safety, environmental friendliness p. marwedel, informatik 12, 2011 - 39 -

Thermal models becoming increasingly important § since temperatures become more relevant due to increased performance, and § since temperatures affect • usability and • dependability. p. marwedel, informatik 12, 2011 - 40 -

Model components § Thermal conductance reflects the amount of heat transferred through a plate (made from that material) of area A and thickness L when the temperatures at the opposite sides differ by one Kelvin. § The reciprocal of thermal conductance is called thermal resistance. § Thermal resistances add up like electrical resistances § Masses storing heat correspond to capacitors Thermal modeling typically uses equivalent electrical models and employs well-known techniques for solving electrical network equations p. marwedel, informatik 12, 2011 - 41 -

Results of simulations based on thermal models (1) Encapsulated cryptographic coprocessor: Source: http: //www. coolingzone. com/Guest/News/ NL_JUN_2001/Campi/Jun_Campi_2001. html p. marwedel, informatik 12, 2011 - 42 -

Results of simulations based on thermal models (2) Microprocessor Source: http: //www. flotherm. com/ applications/app 141/hot_chip. pdf p. marwedel, informatik 12, 2011 - 43 -

Summary § Thiele’s real-time calculus (RTC)/MPA • Using bounds on the number of events in input streams • Using bounds on available processing capability • Derives bounds on the number of events in output streams • Derives bound on remaining processing capability, buffer sizes, … • Examples demonstrate design procedure based on RTC § Energy and power consumption § Thermal behavior p. marwedel, informatik 12, 2011 - 44 -

Some more details p. marwedel, informatik 12, 2011 - 45 -

Analysis – Design Question 3 Architecture D is chosen for further investigation. How should the processors be dimensioned? 113 MIPS NAV 72 kbps (D) 130 MIPS RAD MMI p. marwedel, informatik 12, 2011 © Thiele, ETHZ - 46 -

Analysis – Design Question 3 dmax = 50 29 MIPS 113 MIPS dmax = 200 dmax = 1000 p. marwedel, informatik 12, 2011 72 kbps dmax = 200 NAV 33 MIPS 130 MIPS RAD MMI © Thiele, ETHZ - 47 -

Hamming Distance between adjacent values on the data bus is important p. marwedel, informatik 12, 2011 - 48 -

Other costs Ecpu_data = 5 * w(DAddri) + ß 5 * h(DAddri-1, DAddri) + 6 * w(Datai) + ß 6 * h(Datai-1, Datai) Emem_instr = Min. Cost. Mem(Instr. Mem, Word_widthi) + 7 * w(IAddri) + ß 7 * h(IAddri-1, IAddri) + 8 * w(IDatai) + ß 8 * h(IDatai-1, IDatai) Emem_data = Min. Cost. Mem (Data. Mem, Direction, Word_widthi) + 9 * w(DAddri) + ß 9 * h(DAddri-1, DAddri) + 10 * w(Datai) + ß 10 * h(Datai-1, Datai) p. marwedel, informatik 12, 2011 - 49 -