Graphics Alexandra Nolte Gesine Marwedel 2003 Mapping of

Graphics: © Alexandra Nolte, Gesine Marwedel, 2003 Mapping of Applications to Multi-Processor Systems Peter Marwedel TU Dortmund, Informatik 12 Germany 2011年 12 月 09 日 These slides use Microsoft clip arts. Microsoft copyright restrictions apply.

Application Knowledge Structure of this course 2: Specification 3: ES-hardware 4: system software (RTOS, middleware, …) Design repository 6: Application mapping Design 8: Test 7: Optimization 5: Evaluation & validation (energy, cost, performance, …) Numbers denote sequence of chapters p. marwedel, informatik 12, 2011 - 2 -

The need to support heterogeneous architectures er w o nt p IPE)“ e r e ( “inh iency effic qui nts e r ncy ssista e i c Effi mart a s for Unconventional architectures close to IPE © Renesas, MPSo. C‘ 07 Energy efficiency a key constraint, e. g. for mobile systems red © Hugo De Man/Philips, 2007 p. marwedel, informatik 12, 2011 How to map to these architectures ? - 3 -

Practical problem in automotive design Which processor should run the software? p. marwedel, informatik 12, 2011 - 4 -

A Simple Classification Architecture fixed/ Fixed Architecture to be Auto-parallelizing designed Starting from given task graph Auto-parallelizing Map to CELL, Hopes, COOL codesign tool; Qiang XU (HK) Simunic (UCSD) System. Codesigner Mnemee (Dortmund) Franke (Edinburgh) MAPS Daedalus p. marwedel, informatik 12, 2011 EXPO/SPEA 2 - 5 -

Example: System Synthesis p. marwedel, informatik 12, 2011 © L. Thiele, ETHZ - 6 -

Basic Model – Problem Graph p. marwedel, informatik 12, 2011 © L. Thiele, ETHZ - 7 -

Basic Model: Specification Graph p. marwedel, informatik 12, 2011 © L. Thiele, ETHZ - 8 -

Design Space Scheduling/Arbitration Computation Templates Communication Templates Cipher EDF FPGA RISC SDRAM m. E WFQ DSP TDMA proportional share dynamic fixed priority Look. Up FCFS static Which architecture is better suited for our application? Architecture # 2 Architecture # 1 Look. Up RISC EDF TDMA Priority Cipher DSP WFQ m. E static m. E p. marwedel, informatik 12, 2011 m. E © L. Thiele, ETHZ - 9 -

Evolutionary Algorithms for Design Space Exploration (DSE) p. marwedel, informatik 12, 2011 © L. Thiele, ETHZ - 10 -

Challenges p. marwedel, informatik 12, 2011 © L. Thiele, ETHZ - 11 -

EXPO – Tool architecture (1) MOSES EXPO task graph, scenario graph, flows & resources system architecture performance values SPEA 2 Exploration Cycle selection of “good” architectures p. marwedel, informatik 12, 2011 © L. Thiele, ETHZ - 12 -

EXPO – Tool architecture (2) Tool available online: http: //www. tik. ee. ethz. ch/ex po/expo. html © L. Thiele, ETHZ p. marwedel, informatik 12, 2011 - 13 -

EXPO – Tool (3) p. marwedel, informatik 12, 2011 © L. Thiele, ETHZ - 14 -

Application Model Example of a simple stream processing task structure: p. marwedel, informatik 12, 2011 © L. Thiele, ETHZ - 15 -

Exploration – Case Study (1) p. marwedel, informatik 12, 2011 © L. Thiele, ETHZ - 16 -

Exploration – Case Study (2) p. marwedel, informatik 12, 2011 © L. Thiele, ETHZ - 17 -

Exploration – Case Study (3) p. marwedel, informatik 12, 2011 © L. Thiele, ETHZ - 18 -

More Results Performance for encryption/decryption Performance for RT voice processing p. marwedel, © L. Thiele, ETHZ informatik 12, 2011 - 19 -

Design Space Exploration with System. Co. Designer (Teich et al. , Erlangen) § System Synthesis comprises: • • Resource allocation Actor binding Channel mapping Transaction modeling § Idea: • Formulate synthesis problem as 0 -1 ILP • Use Pseudo-Boolean (PB) solver to find feasible solution • Use multi-objective Evolutionary algorithm (MOEA) to optimize Decision Strategy of the PB solver © J. Teich, U. Erlangen-Nürnberg p. marwedel, informatik 12, 2011 - 20 -

A 3 rd approach based on evolutionary algorithms: SYMTA/S: [R. Ernst et al. : A framework for modular analysis and exploration of heteterogenous embedded systems, Real-time Systems, 2006, p. 124] p. marwedel, informatik 12, 2011 - 21 -

A Simple Classification Architecture fixed/ Fixed Architecture to be Auto-parallelizing designed Starting from given task graph Auto-parallelizing Map to CELL, Hopes COOL codesign tool; Qiang XU (HK) Simunic (UCSD) System. Codesigner Mnemee (Dortmund) Franke (Edinburgh) MAPS Daedalus p. marwedel, informatik 12, 2011 EXPO/SPEA 2 - 22 -

Martino Ruggiero, Luca Benini: Mapping task graphs to the CELL BE processor, 1 st Workshop on Mapping of Applications to MPSo. Cs, Rheinfels Castle, 2008 A fixed architecture approach: Map CELL p. marwedel, informatik 12, 2011 - 23 -

Partitioning into Allocation and Scheduling R p. marwedel, informatik 12, 2011 © Ruggiero, Benini, 2008 - 24 -

p. marwedel, informatik 12, 2011 - 25 -

A Simple Classification Architecture fixed/ Fixed Architecture to be Auto-parallelizing designed Starting from given task graph Auto-parallelizing Map to CELL, Hopes, COOL codesign tool; Qiang XU (HK) Simunic (UCSD) System. Codesigner Mnemee (Dortmund) Franke (Edinburgh) MAPS Daedalus p. marwedel, informatik 12, 2011 EXPO/SPEA 2 - 26 -

Daedalus Design-flow Sequential application Explore, modify, select instances Sesame System-level design space exploration High-level Models Library of IP cores System-Level Specification Common XML Interface RTL-level Models Platform specification Mapping specification Automatic KPNgen Parallelization Parallel application Kahn Process Network specification ESPAM System-level synthesis RTL-Level Specification Ed Deprettere et al. : Toward Composable Multimedia MP-So. C Design, 1 st Workshop on Mapping of Applications to MPSo. Cs, Rheinfels Castle, 2008 Synthesizable VHDL MP-So. C C/C++ code for processors Multi-processor System on Chip Xilinx Platform Studio (XPS) (Synthesizable VHDL and C/C++ code for processors) p. marwedel, informatik 12, 2011 © E. Deprettere, U. Leiden - 27 -

JPEG/JPEG 2000 case study Example architecture instances for a single-tile JPEG encoder: 16 KB Vin, DCT 2 KB 32 KB Q, VLE, Vout Vin, Q, VLE, Vout 2 Micro. Blaze processors (50 KB) DCT, Q 8 KB DCT, Q VLE, Vout Vin DCT 2 KB Q 2 KB Vin 8 KB 2 KB DCT, Q 2 KB 8 KB 32 KB VLE, Vout DCT, Q 4 x 2 KB DCT 1 Micro. Blaze, 1 HW DCT (36 KB) 4 x 2 KB 32 KB 4 KB DCT 2 KB 8 KB Q 2 KB 4 x 16 KB 6 Micro. Blaze processors (120 KB) 4 Micro. Blaze, 2 HW DCT (68 KB) p. marwedel, informatik 12, 2011 © E. Deprettere, U. Leiden - 28 -

Sesame DSE results: Single JPEG encoder DSE p. marwedel, informatik 12, 2011 © E. Deprettere, U. Leiden - 29 -

A Simple Classification Architecture fixed/ Fixed Architecture to be Auto-parallelizing designed Starting from given task graph Auto-parallelizing Map to CELL, Hopes, COOL codesign tool; Qiang XU (HK) Simunic (UCSD) System. Codesigner Mnemee (Dortmund) Franke (Edinburgh) MAPS Daedalus p. marwedel, informatik 12, 2011 EXPO/SPEA 2 - 30 -

Auto-Parallelizing Compilers Discipline “High Performance Computing”: § Research on vectorizing compilers for more than 25 years. § Traditionally: Fortran compilers. § Such vectorizing compilers usually inappropriate for Multi. DSPs, since assumptions on memory model unrealistic: • Communication between processors via shared memory • Memory has only one single common address space De Facto no auto-parallelizing compiler for Multi-DSPs! Work of Franke, O’Boyle (Edinburgh) © Falk p. marwedel, informatik 12, 2011 - 31 -

Introduction of Memory Architecture-Aware Optimization The MACC PMS (Processor/ Memory/Switch) Model § Explicit memory architecture § API provides access to memory information MACC_System C code CPU 1 CPU 2 SPM CPU 3 SPM L 1$ BUS 1 MM 2 BRI L 2$ MM 3 BUS 2 p. marwedel, informatik 12, 2011 - 32 -

Ma. CC Modeling Example via GUI p. marwedel, informatik 12, 2011 - 33 -

Toolflow Detailed View (Sequential C Source Code) START MACC Eco-System (1) Dynamic Data Type Optimizations (2) Map source code to task graphs MPSo. C Parallelization Assistant (MPA) Memory Hierarchy (MH) (4) Dynamic Memory Management Optimizations MNEMEE Toolflow (3) Parallelization Implem. 1. Optimization of dynamic data structures 2. Extraction of potential parallelism 3. Implementation of parallelism; placement of static data 4. Placement of dynamic data p. marwedel, informatik 12, 2011 Page 34 -

Toolflow Detailed View (5) Memory Aware Mapping (6) RTLIB Mapping (7) Scratchpad Memory Optimizations per PE Platform DB END (Optimized Source Code) MNEMEE Toolflow (5) Scenario Based Mapping 5. Perform mapping to processing elements • Scenario based • Memory aware 6. Transform the code to implement the mapping 7. Perform scratchpad memory optimizations for each processing element p. marwedel, informatik 12, 2011 Page 35 -

p. marwedel, informatik 12, 2011 Rainer Leupers, Weihua Sheng: MAPS: An Integrated Framework for MPSo. C Application Parallelization, 1 st Workshop on Mapping of Applications to MPSo. Cs, Rheinfels Castle, 2008 © Leupers, Sheng, 2008 MAPS-TCT Framework - 36 -

Summary § Clear trend toward multi-processor systems for embedded systems, there exists a large design space § Using architecture crucially depends on mapping tools § Mapping applications onto heterogeneous MP systems needs allocation (if hardware is not fixed), binding of tasks to resources, scheduling § Two criteria for classification • Fixed / flexible architecture • Auto parallelizing / non-parallelizing § Introduction to proposed Mnemee tool chain Evolutionary algorithms currently the best choice p. marwedel, informatik 12, 2011 - 37 -