Energy Limits in AD Converters May 25 2012
- Slides: 56
Energy Limits in A/D Converters May 25, 2012 Boris Murmann murmann@stanford. edu
Murmann Mixed-Signal Group 2
Research Overview Large area electronics MEMS Sensor interfaces Digital enhancement algorithms Biomolecule detection Spin-Valve Brain interfaces Medical ultrasound High-performance and low-power A/D and D/A converters 3
ADC Landscape in 2004 B. Murmann, "ADC Performance Survey 1997 -2012, " [Online]. Available: http: //www. stanford. edu/~murmann/adcsurvey. html 4
ADC Landscape in 2012 B. Murmann, "ADC Performance Survey 1997 -2012, " [Online]. Available: http: //www. stanford. edu/~murmann/adcsurvey. html 5
Observation • ADCs have become substantially “greener” over the years • Questions – How much more improvement can we hope for? – What are the trends and limits for today’s popular architectures? – Can we benefit from further process technology scaling? 6
Outline • Fundamental limit • General trend analysis • Architecture-specific analysis – Flash – Pipeline – SAR – Delta-Sigma • Summary 7
Fundamental Limit [Hosticka, Proc. IEEE 1985; Vittoz, ISCAS 1990] 8
ADC Landscape in 2004 4 x/6 d. B 9
ADC Landscape in 2012 4 x/6 d. B 10
Ratio Plot (2004) Technology- or CV 2 -limited regime Noise-limited regime 11
Ratio Plot (2012) ~10, 000 100 x in 8 years ~100 3 -4 x in 8 years 12
Energy by Architecture 13
Flash ADC 2 B-1 Ecomp Eenc • High Speed – Limited by single comparator plus encoding logic • High complexity, high input capacitance – Typically use for resolutions up to 6 bits 14
Encoder • Assume a Wallace encoder (“ones counter”) • Uses ~2 B–B full adders, equivalent to ~ 5∙(2 B–B) gates 15
Matching-Limited Comparator Offset Cc Cc Required capacitance Confidence interval Simple Dynamic Latch Assuming Ccmin = 5 f. F for wires, clocking, etc. 3 d. B penalty accounts for “DNL noise” Matching Energy 16
Typical Process Parameters Process [nm] AVT [m. V-mm] Cox [f. F/mm 2] AVT 2 Cox /k. T Egate [f. J] 250 8 9 139 80 130 4 14 54 10 65 3 17 37 3 32 1. 5 43 23 1. 5 17
Comparison to State-of-the-Art [6] [1] [2] [1] Van der Plas, ISSCC 2006 [2] El-Chammas, VLSI 2010 [3] Verbruggen, VLSI 2008 [3] [4] [5] [4] Daly, ISSCC 2008 [5] Chen, VLSI 2008 [6] Geelen, ISSCC 2001 (!) 18
Impact of Scaling 19
Impact of Calibration (1) • Important to realize that only comparator power reduces Bcal 3 20
Impact of Calibration (2) 21
Ways to Approach Emin (1) • Offset calibrate each comparator – Using trim-DACs [El-Chammas, VLSI 2010] 22
Ways to Approach Emin (2) • Find ways to reduce clock power • Example: resonant clocking (54% below CV 2) [Ma, ESSCIRC 2011] 23
Raison D'Être for Architectures Other than Flash… 24
Pipeline ADC • Conversion occurs along a cascade of stages • Each stage performs a coarse quantization and computes its error (Vres) • Stages operate concurrently – Throughput is set by the speed of one single stage 25
Pipelining – A Very Old Idea 26
Typical Stage Implementation [Abo, 1999] Power goes here 27
Simplified Model for Energy Calculation • Considering the most basic case – Stage gain = 2 1 bit resolution per stage – Capacitances scaled down by a factor of two from stage to stage (first order optimum) – No front-end track-and-hold – Neglect comparator energy 28
Simplified Gain Stage Model Feedback factor Assumptions Closed-loop gain = 2 Infinite transistor f. T (Cgs=0) Thermal noise factor g= 1, no flicker noise Bias device has same noise as amplifier device Linear settling only (no slewing) Effective load capacitance Total integrated output noise 29
Total Pipeline Noise First sampler 30
Key Constraints Thermal noise sets C Settling time sets gm gm sets power 31
Pulling It All Together Settling “Number of t” Excess noise Non-unity feedback factor VDD penalty Supply utilization Transconductor efficiency • For SNDR = {60. . 80}d. B, VDD=1 V, gm/ID=1/(1. 5 k. T/q), Vinpp=2/3 V, the entire expression becomes • For realistic numbers at low resolution, we must introduce a bound for minimum component sizes 32
Energy Bound • Assume that in each stage Ceff > Ceffmin = 50 f. F • For n stages, detailed analysis shows that this leads to a minimum energy of • Adding this overhead to Epipe gives the energy curve shown on the next slide 33
Comparison to State-of-the-Art [4] [2] [3] [6] [5] [1] Verbruggen, ISSCC 2012 [2] Chu, VLSI 2010 [3] Lee, VLSI 2010 [4] Anthony, VLSI 2008 [5] Lee, ISSCC 2012 [6] Hershberg, ISSCC 2012 34
Ways to Approach Emin (1) [Chu, VLSI 2010] • Comparator-based SC circuits replace op-amps with comparators • Current ramp outputs – Essentially “class-B” (all charge goes to load) 35
Ways to Approach Emin (2) [Lee, VLSI 2010] Similar: [Lee, ISSCC 2012] • Use only one residue amplifier • Build sub-ADCs using energy efficient SAR ADCs • Essential idea: minimize overhead as much as possible 36
Ways to Approach Emin (3) [Verbruggen, ISSCC 2012] • Similar to Lee’s architecture (2 -stage using SAR), but with fully dynamic residue amplifier • Class-B-like charge transfer 37
Ways to Approach Emin (4) [Hershberg, ISSCC 2012] • Completely new idea: ring amplifier – As in “ring oscillator” 38
Ways to Approach Emin (5) [Hershberg, ISSCC 2012] • Class-C-like oscillations until charge transfer is complete – Very energy efficient 39
Expected Impact of Technology Scaling • Low resolution (SNDR ~ 40 -60 d. B) – Continue to benefit from scaling – Expect energy reductions due to reduced Cmin and reduction of CV 2 -type contributors • High resolution (SNDR ~ 70 d. B+) – It appears that future improvements will have to come from architectural innovation – Technology scaling will not help much and is in fact often perceived as a negative factor in noise limited designs (due to reduced VDD) • Let’s have a closer look at this… 40
A Closer Look at the Impact of Technology Scaling • As we have shown • Low VDD hurts, indeed, but one should realize that this is not the only factor • Designers have worked hard to maintain (if not improve) Vinpp/VDD in low-voltage designs • How about gm/ID? 41
gm/ID Considerations (1) • Largest value occurs in subthreshold ~(1. 5 k. T/q)-1 • Range of gm/ID does not scale (much) with technology 42
gm/ID Considerations (2) • f. T is small in subthreshold region • Must look at gm/ID for given f. T requirement to compare technologies 43
gm/ID Considerations (3) • Example – f. T = 30 GHz – 90 nm: gm/ID = 18 S/A – 180 nm: gm/ID = 9 S/A • For a given f. T, 90 nm device takes less current to produce same gm – Helps mitigate, if not eliminate penalty due to lower VDD (!) 44
ADC Energy for 90 nm and Below 45
Successive Approximation Register ADC • Input is approximated via a binary search • Relatively low complexity • Moderate speed, since at least B+1 clock cycles are needed for one conversion • Precision is determined by DAC and comparator
Classical Implementation Ecomp Edac B Elogic B [Mc. Creary, JSSC 12/1975] (somewhat optimistic) 47
DAC Energy • Is a strong function of the switching scheme • Excluding adiabatic approaches, the “merged capacitor switching” scheme achieves minimum possible energy [Hariprasath, Electronics Lett. , 4/2010] For 10 bits: 48
DAC Unit Capacitor Size (C) • Is either set by noise, matching, or minimum realizable capacitance (assume Cmin = 0. 5 f. F) • We will exclude matching limitations here, since these can be addressed through calibration • Assuming that one third of the total noise power is allocated for the DAC, we have 49
Comparator Thermal Noise Cc Cc Simple Dynamic Latch (Assuming Ccmin = 5 f. F) Switching probability 50
Comparison to State-of-the-Art [7] [6] [5] [1] Shikata, VLSI 2011 [2] Van Elzakker, ISSCC 2008 [3] Harpe, ISSCC 2012 [4] Liu, VLSI 2010 [2] [3] [4] [5] Liu, ISSCC 2010 [6] Hurrell, ISSCC 2010 [7] Hesener, ISSCC 2007 51
Ways to Approach Emin (1) High Noise Comp Low Noise Comp [Giannini, ISSCC 2008] Dynamic Noise adjustment for comparator power savings 52
Ways to Approach Emin (2) • Minimize unit caps as much as possible for moderate resolution designs – Scaling helps! 0. 5 f. F unit capacitors [Shikata, VLSI 2011] 53
Delta-Sigma ADCs • Discrete time – Energy is dominated by the first-stage switched-capacitor integrator – Energy analysis is similar to that of a pipeline stage • Continuous time – Energy is dominated by the noise and distortion requirements of the first-stage continuous time integrator – Noise sets resistance level, distortion sets amplifier current level – Interestingly, this leads to about the same energy limits as in a discrete-time design 54
Overall Picture 55
Summary • No matter how you look at it, today’s ADCs are extremely well optimized • The main trend is that the “thermal knee” shifts very rapidly toward lower resolutions – Thanks to process scaling and creative design • The high resolution regime is governed by E/Emin ~ 100 – This will be very hard to change – Scaling does not help much – Need to think outside the box and apply more class-B and class-C-type circuitry 56
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