Cpr E 588 Embedded Computer Systems Prof Joseph
Cpr. E 588 Embedded Computer Systems Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #6 – Model Refinement
Communication Synthesis • Bus allocation / protocol selection • Channel partitioning • Protocol, transducer insertion • Inlining Specification model Architecture exploration Architecture model Communication synthesis Communication model Backend Implementation model R. Domer, The Spec. C System-Level Design Language and Methodology, Center for Embedded Systems, University of California-Irvine, 2001. Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 2
Bus Allocation / Channel Partitioning PE 1 PE 2 B 1 • Allocate busses Bus 1 v 1 B 13 snd cb 13 B 13 rcv v 1 B 2 B 3 • Partition channels c 2 B 34 rcv cb 34 B 34 snd • Update communication Ø Additional level of hierarchy to model bus structure Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 3
Model after Channel Partitioning PE 1 PE 2 B 1 Bus 1 v 1 cb 13 B 13 snd c 2 B 13 rcv v 1 cb 34 Feb 17 -19, 2009 B 2 B 34 rcv B 34 snd Cpr. E 588 – Embedded Computer Systems Lect-06. 4
Bus Channel Bus 1 Hierarchical channel: c 2 IBus cb 13 1 cb 34 5 Virtual addressing: 1 10 typedef enum { CB 13, C 2, CB 34 } Bus. Addr; interface IBus { void send( Bus. Addr a, void* d, int size ); void recv( Bus. Addr a, 5 void* d, int size ); }; Feb 17 -19, 2009 void send( Bus. Addr a, { switch( a ) { case CB 13: return case C 2: return case CB 34: return } } void recv( Bus. Addr a, { switch( a ) { case CB 13: return case C 2: return 20 case CB 34: return } } }; 15 Bus interface: 1 channel Bus 1() implements IBus { Ch. MP cb 13, c 2, cb 34; Cpr. E 588 – Embedded Computer Systems void* d, int size ) cb 13. send( d, size ); c 2. send( d, size ); cb 34. send( d, size ); void* d, int size ) cb 13. recv( d, size ); c 2. recv( d, size ); cb 34. recv( d, size ); Lect-06. 5
Model after Channel Partitioning • Leaf behaviors PE 1 1 B 1 5 behavior B 13 Snd( in int v 1, IBus bus 1 { void main(void) { bus. send( bus 1. send(CB 13, &v 1, sizeof(v 1)); ); ) } }; v 1 1 B 13 snd behavior B 2( in int v 1, IBus bus 1 { void main(void) { 5 ) bus 1. send( C 2, ); B 2 } }; 1 B 34 rcv 5 IBusbus 1 behavior B 34 Rcv( IBus { void main(void) { bus. recv( bus 1. recv(CB 34, 0, 0, 0 0); ); ) } }; Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 6
After Channel Partitioning (cont. ) PE 1 B 1 1 5 v 1 B 13 snd B 2 B 34 rcv Feb 17 -19, 2009 behavior PE 1( IBus bus 1 { int v 1; B 1 ( v 1 ); bus 1 B 13 Snd b 13 snd( v 1, bus 1 ); bus 1 ( v 1, bus 1 ); B 2 10 b 1 ) b 2 bus 1 B 34 Rcv b 34 rcv( bus 1 ); void main(void) { b 1. main(); b 13 snd. main(); b 2. main(); b 34 rcv. main(); } 20 }; 15 Cpr. E 588 – Embedded Computer Systems Lect-06. 7
After Channel Partitioning (cont. ) • Leaf behaviors 1 5 IBus bus 1 behavior B 13 Rcv( IBus , out int v 1 ) { void main(void) { bus. send( bus 1. recv(CB 13, &v 1, sizeof(v 1)); ); PE 2 } }; 1 behavior B 3( in int v 1, IBus bus 1 { void main(void) { 5 ) bus 1. recv( C 2, ); B 13 rcv v 1 B 3 } }; 1 5 IBusbus 1 behavior B 34 Snd( IBus { void main(void) { bus. send( bus 1. send(CB 34, 0, 0, 0 0); ); ) B 34 snd } }; Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 8
After Channel Partitioning (cont. ) PE 2 1 behavior PE 2( IBus bus 1 { int v 1; ) 5 bus 1 B 13 Rcv b 13 rcv( bus 1 , v 1 ); B 3 bus 1 ( v 1, bus 1 B 34 Snd b 34 snd( bus 1 ); 10 void main(void) { b 13 rcv. main(); b 34 snd. main(); } 15 v 1 B 3 }; Feb 17 -19, 2009 B 13 rcv B 34 snd Cpr. E 588 – Embedded Computer Systems Lect-06. 9
After Channel Partitioning (cont. ) PE 1 PE 2 B 1 Bus 1 v 1 cb 13 B 13 snd c 2 v 1 cb 34 B 2 B 34 rcv B 13 rcv B 34 snd 1 behavior Design() { Bus 1 bus 1; 5 PE 1 pe 1( bus 1 ); bus 1 PE 2 pe 2( bus 1 ); void main(void) { par { pe 1. main(); pe 2. main(); } } 10 }; Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 10
Protocol Insertion Bus 1 cb 13 Application c 2 Protocol Layer cb 34 Layer • Insert protocol layer • Protocol channel • Create application layer • Implement message-passing over bus protocol • Replace bus channel • Hierarchical combination of application, protocol layers Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 11
Protocol Example • Double handshake protocol address[15: 0] data[31: 0] Master ready Slave ack Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 12
Protocol Example (cont. ) • Timing diagram address[15: 0] data[31: 0] ready ack (5, 15) (5, 25) (10, 20) Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems (5, 15) Lect-06. 13
Protocol Layer IProtocol. Master address[15: 0] data[31: 0 ] read y ack IProtocol. Slave Dbl. HSProtocol • Protocol channel • Encapsulate wires • Abstract bus transfers • Implement protocol • Bus timing Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 14
Protocol Channel Dbl. HSProtocol IProtocol. Slave IProtocol. Master channel Dbl. HSProtocol() implements IProtocol. Master, IProtocol. Slave { bit[15: 0] address; 5 bit[31: 0] data; Signal ready(); Signal ack(); 1 address[15: 0] data[31: 0 ] read y ack 10 }; Master interface: Slave interface: interface IProtocol. Master { void master. Write( bit[15: 0] bit[31: 0] void master. Read( bit[15: 0] 5 bit[31: 0] }; 1 Feb 17 -19, 2009 interface IProtocol. Slave { void slave. Write( bit[15: 0] bit[31: 0] void slave. Read( bit[15: 0] 5 bit[31: 0] }; 1 a, d ); a, *d ); Cpr. E 588 – Embedded Computer Systems a, d ); a, *d ); Lect-06. 15
Protocol Master Interface address[15: 0] data[31: 0] ready ack (5, 15) (5, 25) (10, 20) void master. Read( bit[15: 0] a, bit[31: 0] *d ) { do { t 1: address = a; waitfor( 5 ); // estimated delay 5 t 2: ready. set( 1 ); ack. waituntil( 1 ); t 3: *d = data; waitfor( 15 ); // estimated delay t 4: ready. set( 0 ); 10 ack. waituntil( 0 ); } timing { // constraints range( t 1; t 2; 5; 15 ); range( t 3; t 4; 10; 25 ); } 15 } 1 Feb 17 -19, 2009 (5, 15) void master. Write( bit[15: 0] a, bit[31: 0] d ) { do { t 1: address = a; data = d; 5 waitfor( 5 ); // estimated delay t 2: ready. set( 1 ); ack. waituntil( 1 ); t 3: waitfor( 10 ); // estimated delay t 4: ready. set( 0 ); 10 ack. waituntil( 0 ); } timing { // constraints range( t 1; t 2; 5; 15 ); range( t 3; t 4; 10; 25 ); } 15 } 1 Cpr. E 588 – Embedded Computer Systems Lect-06. 16
Protocol Slave Interface address[15: 0] data[31: 0] ready ack (5, 15) (5, 25) (10, 20) void slave. Read( bit[15: 0] a, bit[31: 0] *d ) { do { t 1: ready. waituntil( 1 ); t 2: if( a != address ) goto t 1; 5 *d = data; waitfor( 12 ); // estimated delay t 3: ack. set( 1 ); ready. waituntil( 0 ); t 4: waitfor( 7 ); // estimated delay 10 t 5: ack. set( 0 ); } timing { // constraints range( t 2; t 3; 10; 20 ); range( t 4; t 5; 5; 15 ); } 15 } 1 Feb 17 -19, 2009 (5, 15) void slave. Write( bit[15: 0] a, bit[31: 0] d ) { do { t 1: ready. waituntil( 1 ); t 2: if( a != address ) goto t 1; 5 data = d; waitfor( 12 ); // estimated delay t 3: ack. set( 1 ); ready. waituntil( 0 ); t 4: waitfor( 7 ); // estimated delay 10 t 5: ack. set( 0 ); } timing { // constraints range( t 2; t 3; 10; 20 ); range( t 4; t 5; 5; 15 ); } 15 } 1 Cpr. E 588 – Embedded Computer Systems Lect-06. 17
Application Layer IBus. Slave Dbl. HSProtocol IProtocol. Slave IProtocol. Master IBus. Master Application channel • Implement abstract message-passing over protocol • Synchronization • Arbitration • Addressing • Data slicing Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 18
Application Layer (cont. ) Send/receive data block Computation Behavior Comm. /channel call Computation Message-passing Application Layer Sync intr/poll. . . Arbitration req/ack Read/write meta data Bus read/write ID 1 ID 2 Protocol. . . call IDn Read/write data words Sync/arbitr. data 1 data 2. . . data. . . m release Bus transfer Protocol Layer Feb 17 -19, 2009 addr[] data[] ctrl[] Cpr. E 588 – Embedded Computer Systems Lect-06. 19
Application Layer Channel Dbl. HSBus channel Dbl. HSBus() implements IBus. Master, IBus. Slave { Dbl. HSProtocol protocol; 5 IBus. Slave Dbl. HSProtocol IProtocol. Slave IProtocol. Master IBus. Master 1 }; Master interface: Slave interface: interface IBus. Master { void master. Send( Bus. Addr a, void* d, int size ); void master. Recv( Bus. Addr a, 5 void *d, int size ); }; 1 Feb 17 -19, 2009 interface IBus. Slave { void slave. Send( Bus. Addr a, void* d, int size ); void slave. Recv( Bus. Addr a, 5 void* d, int size ); }; 1 Cpr. E 588 – Embedded Computer Systems Lect-06. 20
Application Layer Methods Master interface: 1 Slave interface: void master. Send( int a, void* d, int size ) { long *p = d; for( ; size > 0; size -= 4, p++ ) { protocol. master. Write( a, *p ); } 5 1 } void master. Recv( int a, void* d, int size ) { long *p = d; for( ; size > 0; size -= 4, p++ ) { protocol. master. Read( a, p ); } 15 for( ; size > 0; size -= 4, p++ ) { protocol. slave. Write( a, *p ); } 5 } 10 void slave. Send( int a, void* d, int size ) { long *p = d; } Feb 17 -19, 2009 10 void slave. Recv( int a, void* d, int size ) { long *p = d; for( ; size > 0; size -= 4, p++ ) { protocol. slave. Read( a, p ); } 15 } Cpr. E 588 – Embedded Computer Systems Lect-06. 21
Model after Protocol Insertion Master Slave PE 1 PE 2 B 1 IBus. Slave address[15: 0] data[31: 0] ready ack IProtocol. Slave B 13 snd Dbl. HSProtocol IProtocol. Master v 1 IBus. Master Dbl. HSBus B 13 rcv v 1 B 2 B 34 rcv B 34 snd Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 22
Model after Protocol Insertion (cont. ) • Leaf behaviors PE 1 B 1 1 5 behavior B 13 Snd( in int v 1, IBus. Master bus 1 { void main(void) { bus. send( CB 13, &v 1, sizeof(v 1) ); bus 1. master. Send(CB 13, &v 1, sizeof(v 1) ); ) } }; v 1 B 13 snd 1 behavior B 2( in int v 1, IBus. Master bus 1 { void main(void) { 5 ) bus 1. master. Send( C 2, ); B 2 } }; 1 B 34 rcv 5 behavior B 34 Rcv( IBus. Masterbus 1 { void main(void) { bus. recv( CB 34, 0, 0 ); bus 1. master. Recv( CB 34, ) } }; Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 23
Model after Protocol Insertion (cont. ) PE 1 1 B 1 5 v 1 B 13 snd B 34 rcv Feb 17 -19, 2009 B 1 15 20 b 1 ); bus 1 ( v 1, bus 1 ); b 2 ) ( v 1 ); bus 1 B 13 Snd b 13 snd( v 1, bus 1 B 2 10 B 2 behavior PE 1( IBus. Master bus 1 { int v 1; bus 1 B 34 Rcv b 34 rcv( bus 1 ); void main(void) { b 1. main(); b 13 snd. main(); b 2. main(); b 34 rcv. main(); } }; Cpr. E 588 – Embedded Computer Systems Lect-06. 24
Model after Protocol Insertion (cont. ) • Leaf behaviors 1 5 IBus. Slave bus 1 behavior B 13 Rcv( IBus. Slave , out int v 1 ) { void main(void) { bus. slave. Send( bus 1. slave. Recv(CB 13, &v 1, sizeof(v 1)); ); PE 2 } }; 1 behavior B 3( in int v 1, IBus. Slave bus 1 { void main(void) { 5 ) bus 1. slave. Recv( C 2, ); B 13 rcv v 1 B 3 } }; 1 5 IBus. Slavebus 1 behavior B 34 Snd( IBus. Slave { void main(void) { bus 1. slave. Send( CB 34, 0, 0, 0 0 ); ); ) B 34 snd } }; Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 25
Model after Protocol Insertion (cont. ) PE 2 1 behavior PE 2( IBus. Slave bus 1 { int v 1; bus 1 B 13 Rcv b 13 rcv( bus 1 5 B 3 b 3 , v 1 ); bus 1 ( v 1, bus 1 B 34 Snd b 34 snd( bus 1 ) ); 10 v 1 void main(void) { b 13 rcv. main(); b 34 snd. main(); } 15 }; Feb 17 -19, 2009 B 13 rcv ); B 34 snd Cpr. E 588 – Embedded Computer Systems Lect-06. 26
Model after Protocol Insertion (cont. ) PE 1 PE 2 B 1 B 2 B 34 rcv 1 address[15: 0] data[31: 0] ready ack IBus. Slave B 13 snd Dbl. HSProtocol IProtocol. Slave v 1 IProtocol. Master IBus. Master Dbl. HSBus v 1 B 3 behavior Design() { Dbl. HSBus bus 1; Dble. HSBus bus 1(); bus 1 PE 1 pe 1( bus 1 ); bus 1 PE 2 pe 2( bus 1 ); 5 B 13 rcv B 34 snd void main(void) { par { pe 1. main(); pe 2. main(); } } 10 }; Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 27
Intellectual Property (IP) PE 2 B 13 rcv IP Components IP 2 v 1 B 34 snd • Functionality of B 3 • Quality metrics • IP component library • Pre-designed components • Fixed functionality • Fixed interface / protocols • Allocate IP components • Implement functionality through IP reuse Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 28
IP Component Model IIPBus IP 2 • Component behavior • Simulation, synthesis interface IIPBus { void start( int v 1, ); void done( void ); }; 5 1 • Wrapper • Encapsulate fixed IP protocol • Provide canonical interface Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 29
Transducer Insertion PE 1 PE 2 B 1 T 1 IP 2 B 13 rcv v 1 IIPBus IBus. Slave address[15: 0] data[31: 0] ready ack IProtocol. Slave B 13 snd IProtocol. Master v 1 IBus. Master Dbl. HSBus B 2 B 34 rcv B 34 snd Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 30
Transducer 1 T 1 behavior T 1( IBus. Slave bus, IIPbus ip ) { int v 1, ; 5 void main(void) { bus. slave. Receive( CB 13, &v 1, sizeof(v 1) ); bus. slave. Receive( C 2, ); ip. start( v 1, ); 10 ip. done(); bus. slave. Send( CB 34, 0, 0 ); } }; • Translate between protocols • Send / receive messages • Buffer in local memory Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 31
Inlining PE 1 IBus. Slave Feb 17 -19, 2009 address[15: 0] data[31: 0] ready ack Cpr. E 588 – Embedded Computer Systems IProtocol. Slave PE 2 Bus PE 2 Protocol PE 1 Protocol IProtocol. Master PE 1 Bus PE 2 IBus. Slave address[15: 0] data[31: 0] ready ack IProtocol. Slave IProtocol. Master IBus. Master Dbl. HSProtocol • Create bus interfaces and drivers • Refine communication IBus. Master PE 1 PE 2 Dbl. HSBus Lect-06. 32
Model after Inlining PE 2 PE 1 B 1 v 1 B 13 snd address[15: 0] data[31: 0] B 13 rcv ready v 1 ack Feb 17 -19, 2009 B 2 B 34 rcv B 34 snd Cpr. E 588 – Embedded Computer Systems Lect-06. 33
Model after Inlining (cont. ) • PE 1 bus driver Application layer: channel PE 1 Bus( out bit[15: 0] addr. inout bit[31: 0] data, OSignal ready, ISignal ack ) implements IBus. Master 5 { PE 1 Protocol protocol( addr, data, ready, ack ); 1 PE 1 Protocol IProtocol. Master IBus. Master PE 1 Bus addr[15: 0] data[31: 0] ready ack void master. Send( int a, void* d, int size ) { } void master. Recv( int a, void* d, int size ) { } 10 }; Protocol layer: channel PE 1 Protocol( out bit[15: 0] addr. inout bit[31: 0] data, OSignal ready, ISignal ack ) implements IProtocol. Master 5 { void master. Write( bit[15: 0] a, bit[31: 0] d ) { } void master. Read( bit[15: 0] a, bit[31: 0] *d ) { } }; 1 Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 34
Model after Inlining (cont. ) PE 1 behavior PE 1( out bit[15: 0] addr, inout bit[31: 0] data, OSignal ready, ISignal ackack ) 5 { PE 1 Bus bus 1( addr, data, ready, ack ); ); PE 1 Bus 1 v 1 B 13 snd B 2 B 34 rcv Feb 17 -19, 2009 PE 1 Bus B 1 int v 1; 10 15 20 B 13 Snd B 2 B 34 Rcv b 1 ( b 13 snd( b 2 ( b 34 rcv( v 1 ); v 1, bus 1 ); void main(void) { b 1. main(); b 13 snd. main(); b 2. main(); b 34 rcv. main(); } }; Cpr. E 588 – Embedded Computer Systems Lect-06. 35
Model after Inlining (cont. ) • PE 2 bus interface Application layer: channel PE 2 Bus( in bit[15: 0] addr. inout bit[31: 0] data, ISignal ready, OSignal ack ) implements IBus. Slave 5 { PE 2 Bus. Interface protocol( addr, data, ready, ack ); 1 IBus. Slave }; IProtocol. Slave 10 addr[15: 0] data[31: 0] ready ack PE 2 Protocol void slave. Send( int a, void* d, int size ) { } void slave. Recv( int a, void* d, int size ) { } PE 2 Bus Protocol layer: channel PE 2 Protocol( in bit[15: 0] addr. inout bit[31: 0] data, ISignal ready, OSignal ack ) implements IProtocol. Slave 5 { void slave. Write( bit[15: 0] a, bit[31: 0] d ) { } void slave. Read( bit[15: 0] a, bit[31: 0] *d ) { } }; 1 Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 36
Model after Inlining (cont. ) PE 2 int v 1; B 13 Rcv b 13 rcv( bus 1, v 1 ); B 3 b 3 ( v 1, bus 1 ); B 34 Snd b 34 snd( bus 1 ); 10 PE 2 Bus in bit[15: 0] addr, 1 behavior PE 2( in inout bit[31: 0] data, ISignal ready, OSignal ack ) 5 { PE 2 Bus bus 1( addr, data, ready, ack ); ); PE 2 Bus }; Feb 17 -19, 2009 v 1 B 3 void main(void) { b 13 rcv. main(); b 34 snd. main(); } 15 B 13 rcv B 34 snd Cpr. E 588 – Embedded Computer Systems Lect-06. 37
Model after Inlining (cont. ) PE 2 PE 1 B 1 PE 2 Bus B 13 snd address[15: 0] data[31: 0] PE 1 Bus v 1 ready ack B 13 rcv v 1 B 3 B 2 behavior Design() { // wires // bit[15: 0] addr; bit[31: 0] data; 5 bit[31: 0] data; Signal ready; Signal ack; 1 B 34 rcv B 34 snd addr, data, ready, ack PE 1 pe 1( addr, ); addr, data, ready, ack PE 2 pe 2( addr, ); 10 void main(void) { par { pe 1. main(); pe 2. main(); } } 15 }; Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 38
Communication Model • Component & bus structure/architecture • Top level of hierarchy • Bus-functional component models • Timing-accurate bus protocols • Behavioral component description • Timed • Estimated component delays Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Specification model Architecture exploration Architecture model Communication synthesis Communication model Backend Implementation model Lect-06. 39
Backend Specification model • Clock-accurate implementation of PEs Architecture exploration Architecture model • Hardware synthesis Communication synthesis • Software development Communication model • Interface synthesis Backend Implementation model Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 40
Hardware Synthesis PE 2 B 13 rcv v 1 PE 2_CLK Clock boundaries B 3 PE 2_CLK B 34 snd • Schedule operations into clock cycles • Define clock boundaries in leaf behavior C code • Create FSMD model from scheduled C code Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 41
Scheduled Hardware Model 1 Hierarchical FSMD: behavior B 3( in int v 1, IBus. Slave bus ) { void main(void) { enum { S 0, S 1, S 2, , Sn } state = S 0; 5 while( state != Sn ) { waitfor( PE 2_CLK ); v 1 += v 2 slave. Receive() f 3( v 1, v 2, … ) switch( state ) { case Si: v 1 += v 2; // data-path operations if( v 1 ) state = S i+1; else state = S i+2; break; case Si+1: // receive message bus. slave. Receive( C 2, ); state = S i+2; break; case Si+2: f 3( v 1, v 2, … ); state = S i+3; break; 10 Si v 1 != 0 // wait for clock period 15 Si+2 20 25 }} 30 Feb 17 -19, 2009 } }; Cpr. E 588 – Embedded Computer Systems Lect-06. 42
Software Synthesis PE 1 B 1 v 1 B 13 snd B 2 Ff 2 MOVE r 0, r 1 SHL ADD INC r 3 r 2, r 3, r 4 r 2 PUSH CALL POP r 1 Ff 3 r 0 B 34 rcv • Implement behavior on processor instruction-set • Code generation • Compilation Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 43
Code Generation PE 1 B 1 v 1 Code B 13 snd B 2 B 34 rcv Generator 1 void B 1( int *v 1 ) { } 5 void B 13 Snd( int v 1 ) { master. Send( CB 13, &v 1, sizeof(v 1) ); } void B 2( int v 1 ) { 10 master. Send( C 2, ); } 15 void B 34 Rcv( void ) { master. Receive( CB 34, 0, 0 ); } void main(void) 20 { int v 1; B 1( &v 1 ); B 13 Snd( v 1 ); B 2( v 1 ); B 34 Rcv(); 25 } Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 44
Compilation void b 1( int *v 1 ) { } void b 13 snd( int v 1 ) { master. Send( CB 13, &v 1, 5 sizeof(v 1) ); } void b 2( int v 1 ) { master. Send( C 2, ); 10 } void b 34 rcv() { master. Receive( CB 34, 0, 0 ); } 15 1 Target C OBJ Compiler void main(void) { int v 1; b 1( &v 1 ); b 13 send( v 1 ); 20 b 2( v 1 ); b 34 rcv(); } Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 45
Interface Synthesis IBus. Slave addr[15: 0] data[31: 0] ready ack IProtocol. Slave addr[15: 0] data[31: 0] ready ack PE 2 Bus PE 2 Protocol S 3 PE 1 Protocol S 2 IBus. Master S 1 IProtocol. Master PE 1 Bus S 0 DRV S 4 • Implement communication on components • Hardware bus interface logic • Software bus drivers Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 46
Hardware Interface Synthesis • Specification: timing diagram / constraints address[15: 0] data[31: 0] ready ack (10, 20) (5, 15) Ø FSMD implementation: clock cycles 5 CLK address[15: 0] data[31: 0] ready ack State Feb 17 -19, 2009 S 0 S 1 S 2 S 3 Cpr. E 588 – Embedded Computer Systems S 3 S 4 Lect-06. 47
Hardware Interface FSMD size > 0 S 4 = 0 S 3 ready ac k ze ack = = si 1 ze -1 S 2 si !ready && addr != a ta d+ = + *d S 1 da S 0 5 CLK address[15: 0] data[31: 0] ready ack State Feb 17 -19, 2009 S 0 S 1 S 2 S 3 Cpr. E 588 – Embedded Computer Systems S 3 S 4 Lect-06. 48
Hardware Interface FSMD (cont. ) 1 5 10 15 20 25 30 channel PE 2 Bus( in bit[15: 0] addr, inout bit[31: 0] data, ISignal ready, OSignal ack ) implements IBus. Slave { void slave. Send( int a, void* d, int size ) { enum { S 0, S 1, S 2, S 3, S 4, S 5 } state = S 0; while( state != S 5 ) { waitfor( PE 2_CLK ); // wait for clock period switch( state ) { case S 0: // sample ready, address if( (ready. val() == 1) && (addr == a) ) state = S 1; break; case S 1: // read memory, drive data bus data = *( ((long*)d)++ ); state = S 2; break; case S 2: // raise ack, advance counter ack. set( 1 ); size--; state = S 3; break; case S 3: // sample ready if( ready. val() == 0 ) state = S 4; break; case S 4: // reset ack, loop condition ack. set( 0 ); if( size != 0 ) state = S 0 else state = S 5; }} } void slave. Receive( int a, void* d, int size ) { } }; Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems !ready && addr != a data = *d d++ ack = 1 size = size - 1 ready ack = 0 S 1 S 2 size > 0 S 3 S 4 Lect-06. 49
Software Interface Synthesis • Implement communication over processor bus • Map bus wires to processor ports • Match with processor ports • Map to general I/O ports • Generate assembly code • Protocol layer: bus protocol timing via processor’s I/O instructions • Application layer: synchronization, arbitration, data slicing • Interrupt handlers for synchronization Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 50
Software Interface Driver Bus driver: Fmaster. Write ; protocol OUTA r 0 ; OUTB r 1 ; OUTC #0001 ; MOVE ack_event, r 2 5 CALL Fevent_wait ; OUTC #0000 ; RET 1 µProcessor PORTA PORTB PORTC INTA address[15: 0] data[31: 0] ready ack layer write addr write data raise ready wait for ack ev. lower ready Fmaster. Send ; application layer LOOP L 1 END, r 2 ; loop over data MOVE (r 6)+, r 1 CALL Fmaster. Write ; call protocol L 1 END RET 15 10 Interrupt handler: Finta. Handler PUSH r 2 MOVE ack_event, r 2 CALL Fevent_notify POP r 2 5 RTI 1 Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems ; notify ack ev. Lect-06. 51
Implementation Model Software processor Custom hardware PE 1 PE 2 OBJ Instruction Set Simulator (ISS) PORTA address[15: 0] PORTB data[31: 0] PORTC ready INTA ack S 0 S 1 S 2 S 3 S 4 PE 1_CLK Feb 17 -19, 2009 PE 2_CLK Cpr. E 588 – Embedded Computer Systems Lect-06. 52
Implementation Model (cont. ) 1 PE 1 OBJ PORTA Instruction Set Simulator (ISS) PORTB PORTC INTA address[15: 0] data[31: 0] #include <iss. h> behavior PE 1( out bit[15: 0] addr, inout bit[31: 0] data, OSignal ready, 5 ISignal ack ) { void main(void) { // initialize ISS, load program 10 iss. startup(); iss. load("a. out"); // run simulation for( ; ; ) { // drive inputs iss. porta = addr; iss. portb = data; iss. inta = ack. val(); 15 ready ack // ISS API 20 // run processor cycle iss. exec(); waitfor( PE 1_CLK ); PE 1_CLK // update outputs data = iss. portb; ready. set( iss. portc & 0 x 01 ); 25 } 30 Feb 17 -19, 2009 } }; Cpr. E 588 – Embedded Computer Systems Lect-06. 53
Implementation Model (cont. ) behavior PE 2( in bit[15: 0] addr, inout bit[31: 0] data, ISignal ready, OSignal ack ) 5 { // Interface FSM PE 2 Bus bus 1( addr, data, ready, ack ); PE 2 1 int v 1; // memory B 13 Rcv b 13 rcv( bus 1, v 1 ); B 3 b 3 ( v 1, bus 1 ); B 34 Snd b 34 snd( bus 1 ); // FSMDs 10 void main(void) { b 13 rcv. main(); b 34 snd. main(); } 15 20 S 0 addr[15: 0] S 1 data[31: 0] S 2 ready S 3 ack S 4 PE 2_CLK }; Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 54
Implementation Model (cont. ) PE 1 Instruction Set Simulator (ISS) PE 2 PORTA address[15: 0] PORTB data[31: 0] PORTC ready INTA ack S 0 S 1 S 2 S 3 S 4 OBJ PE 1_CLK PE 2_CLK behavior Design() { bit[15: 0] addr; bit[31: 0] data; Signal ready; Signal ack; 5 1 PE 1 pe 1( address, data, ready, ack ); PE 2 pe 2( address, data, ready, ack ); void main(void) { par { pe 1. main(); pe 2. main(); } } 10 }; Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 55
Implementation Model (cont. ) • Cycle-accurate system description • RTL description of hardware • Behavioral/structural FSMD view • Object code for processors • Instruction-set co-simulation • Clocked bus communication • Bus interface timing based on PE clock Feb 17 -19, 2009 Specification model Architecture exploration Architecture model Communication synthesis Communication model Backend Implementation model Cpr. E 588 – Embedded Computer Systems Lect-06. 56
Summary and Conclusions • Spec. C system-level design methodology & language • Four levels of abstraction • • Specification model: untimed, functional Architecture model: estimated, structural Communication model: timed, bus-functional Implementation model: cycle-accurate, RTL/IS • Specification to RTL • System synthesis 1. Architecture exploration (map computation to components) 2. Communication synthesis (map communication to busses) • Backend 3. hardware synthesis, software compilation, interface synthesis • Well-defined, formal models & transformations • Automatic, gradual refinement • Executable models, testbench re-use • Simple verification Feb 17 -19, 2009 Cpr. E 588 – Embedded Computer Systems Lect-06. 57
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