9 Computer Systems Architecture Morris Mano Ref http

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9. 파이프라인과 벡터 처리 Computer Systems Architecture Morris Mano Ref: http: //archi. snu. ac.

9. 파이프라인과 벡터 처리 Computer Systems Architecture Morris Mano Ref: http: //archi. snu. ac. kr/COURSES/ http: //kmh. yeungnam-c. ac. kr/com. Intro/mano/

Sequential Processing

Sequential Processing

Pipelined Processing

Pipelined Processing

세그먼트 실행시간 비교 n Sequential Execution n Pipelined Execution 50 ns 60 ns

세그먼트 실행시간 비교 n Sequential Execution n Pipelined Execution 50 ns 60 ns

5 Segment Pipeline n n n 1. 2. 3. 4. 5. Instruction fetch step

5 Segment Pipeline n n n 1. 2. 3. 4. 5. Instruction fetch step (IF) Instruction decode/register fetch step (ID) Execution/effective address step (EX) Memory access/branch completion step (MEM) Register write-back step (WB)

Structural Hazard IF ID EX MEM WB

Structural Hazard IF ID EX MEM WB

Structural Hazard resource conflict

Structural Hazard resource conflict

Data Hazard (RAW) ADD R 1, R 2, R 3 SUB R 4, R

Data Hazard (RAW) ADD R 1, R 2, R 3 SUB R 4, R 1, R 5 IF ID R IF EX MEM ID EX R Time WB W MEM WB W

Data Hazard 해결 n Freezing the Pipeline n (Internal) Operand Forwarding n Compiler Scheduling

Data Hazard 해결 n Freezing the Pipeline n (Internal) Operand Forwarding n Compiler Scheduling

(Internal) Forwarding

(Internal) Forwarding

Compiler Scheduling n 지연된 로드 (delayed load) n n 컴파일러를 통해서 충돌문제를 해결하는 것으로

Compiler Scheduling n 지연된 로드 (delayed load) n n 컴파일러를 통해서 충돌문제를 해결하는 것으로 데이타 충돌을 감지하고 충돌된 데이터의 참조가 지연되도록 명 령어들을 재배치 (ex) LW LW ADD Naive Code SW LW LW SUB SW a = b + c; d = e - f; Rb, b Rc, c Ra, Rb, Rc a, Ra Re, e Rf, f Rd, Re, Rf d, Rd Scheduled Code LW LW LW ADD LW SW SUB SW Rb, b Rc, c Re, e Ra, Rb, Rc Rf, f a, Ra Rd, Re, Rf d, Rd

Data Hazard 종류 실행 순서: Task(i) Task(j) n n n RAW n j tries

Data Hazard 종류 실행 순서: Task(i) Task(j) n n n RAW n j tries to read a source before i writes it n So j incorrectly gets the old value WAR n j tries to write a destination before it is read by i n So i incorrectly gets the new value WAW n j tries to write an operand before it is written by i n The write being performed in the wrong order

Control Hazard n 원인: PC 레지스터 값의 변화 (instruction 수행순서 변화) n Branch, Jump,

Control Hazard n 원인: PC 레지스터 값의 변화 (instruction 수행순서 변화) n Branch, Jump, Call/Return For 5 -stage pipeline, 3 cycle penalty 15% branch frequency. CPI = 1. 45

Control Hazard 해결 n Optimized branch processing n Branch prediction (분기 예측) n Delayed

Control Hazard 해결 n Optimized branch processing n Branch prediction (분기 예측) n Delayed branch (지연된 분기)

Optimized Branch 1. Find out branch taken or not early -> simplified branch condition

Optimized Branch 1. Find out branch taken or not early -> simplified branch condition 2. Compute branch target address early -> extra hardware 3. Read both addresses (taken or not)

Branch Prediction (ex) Predict-not-taken

Branch Prediction (ex) Predict-not-taken

Delayed Branch n Semantics of delayed branch

Delayed Branch n Semantics of delayed branch

Delayed Branch

Delayed Branch

Delayed Branch • Delayed branch로 인한 이득

Delayed Branch • Delayed branch로 인한 이득

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