Computer System Architecture THIRD EDITION M Morris Mano

Computer System Architecture (THIRD EDITION) M. Morris Mano PRENTICE HALL Computer System Architecture Chap. 1 Digital Logic Circuits Ref: bazi. pe. kr

최초의 컴퓨터 ? n ENIAC (1946) Computer System Architecture Chap. 1 Digital Logic Circuits 2

Von Neumann Architecture n John von Neumann & EDVAC Computer System Architecture Chap. 1 Digital Logic Circuits 3

Quiz Computer System Architecture Chap. 1 Digital Logic Circuits 4

5 n Alan Turing (1912 -1954) Computer System Architecture Chap. 1 Digital Logic Circuits

AI Assistant n AMAZON – Alexa, Google Assistant, SK-NUGU (Aria) n u https: //www. youtube. com/watch? v=xf. Itj. WHJ-Gk u https: //www. youtube. com/watch? v=CBe. Ds. Jie 6 qk u https: //www. youtube. com/watch? v=FDPg 7 fv 24 UQ Computer System Architecture Chap. 1 Digital Logic Circuits 6

Class Overview n 7 Contents u Basic Computer Hardware Architecture u CPU, Memory, I/O System Design u Advanced Topics: Pipeline, Multiprocessor n Related Subject u Digital Logic (논리설계), Discrete Mathematics (이산수학) n Chapter Outline u u u n Ch. 1 ~ Ch. 4: Digital Computer Hardware Architecture Ch. 5 ~ Ch. 7: Basic Computer Design Ch. 8 ~ Ch. 10: CPU Architecture and Pipeline Processing Ch. 11 ~ Ch. 12: I/O and Memory Architecture Ch. 13: Multiprocessor Homework u Solve the selected number of problems u Report of Survey for given theme n Reference u Morris Mano, Computer Systems Architecture, Prentice-Hall, 3 rd Ed. u John Hennessy, David Patterson, Computer Architecture: a Quantitative approach, Morgan Kaufmann. 3 rd Ed. Computer System Architecture Chap. 1 Digital Logic Circuits

A Simple Picture Computer System Architecture Chap. 1 Digital Logic Circuits 8

9 1 -1 Digital Computers n n n Digital – A limited number of discrete value Bit – A Binary Digit Program – A Sequence of instructions API Computer = H/W + S/W Program(S/W) u. A sequence of instruction u. S/W = Program + Data l The data that are manipulated by the program constitute the data base u. Application S/W l DB, word processor, Spread Sheet, game u. System S/W l OS, Firmware, Compiler, Device Driver Computer System Architecture Application S/W Chap. 1 Digital Logic Circuits Operating System ROM BIOS Computer H/W

10 1 -1 Digital Computers n Computer Hardware u CPU u Memory l Program Memory(ROM) l Data Memory(RAM) Memory u I/O Device l Input Device: Keyboard, Mouse, Scanner l CPU Output Device: Printer, Plotter, Display l Storage Device(I/O): FDD, HDD, MOD Input Device Interface Output Device Figure 1 -1 Block Diagram of a digital Computer System Architecture Chap. 1 Digital Logic Circuits

11 Example: Recipe Program code : Set of instructions UI/UX Data Ref) http: //www. eatsamazing. co. uk/recipes-tutorials/cooking-with-small-child-homemade-burgers Computer System Architecture Chap. 1 Digital Logic Circuits

1 -1 Digital Computers n What is “Computer Architecture”? - Hennessy and Patterson, Computer Organization and Design(1990) u Computer Architecture l Instruction Set Architecture (ISA) l Machine Organization n “ISA”? u Instructions u Addressing modes u Instruction and data formats u Register n “Machine Organization”? u CPU(Control, Data path), Memory, Input, Output Computer System Architecture Chap. 1 Digital Logic Circuits 12

13 1 -2 Logic Gates n ADC(Analog to Digital Conversion) u Signal Physical Quantity V, A, F, 거리 n Binary Information Discrete Value Gate 0 : 0. 5 1: 3 u The manipulation of binary information is done by logic circuit called “gate”. n Fig. 1 -2 Digital Logic Gates u AND, OR, INVERTER, BUFFER, NAND, NOR, XNOR n George Boole u Born: 2 Nov 1815 in Lincoln, Lincolnshire, England u Died: 8 Dec 1864 in Ballintemple, County Cork, Ireland Computer System Architecture Chap. 1 Digital Logic Circuits

14 Boole Logic - Example n What is it? u Input, Output 이 이진변수(binary variable)로 구성된 논리 회로 n 우주회 (雨酒會) u 비가 오면 술 먹는다 u 비가 안 오면 술 안 먹는다 A u 비가 온다 : A = 1, 비가 안 온다 : A = 0 u 술 먹는다 : X = 1, 술 안 먹는다 : X = 0 u If (A == 1), Then X = 1; Else, X = 0; X Computer System Architecture Chap. 1 Digital Logic Circuits

Boole Logic - Example 15 http: //nogwon. blogspot. kr/2013/10/blog-post_2036. html Computer System Architecture Chap. 1 Digital Logic Circuits

16 Boole Logic - Example n 비(A)가 오고 친구(B)가 있으면 술(X) 먹는다 u If (A==1)&&(B==1), Then X = 1; Else, X = 0; A X B n 비(A)가 오고 친구(B)가 있고 돈(C)이 있으면 술(X) 먹는다 u If (A==1)&&(B==1)&&(C==1), Then X = 1; Else, X = 0; A B C Computer System Architecture X Chap. 1 Digital Logic Circuits

1 -2 Logic Gates Computer System Architecture Chap. 1 Digital Logic Circuits 17

1 -2 Logic Gates Computer System Architecture Chap. 1 Digital Logic Circuits 18

1 -3 Boolean Algebra n 19 Boolean Algebra u binary variable(A, B, x, y: T/F or 1/0) + logic operation(AND, OR, NOT…) n Boolean Function: variable + operation u F(x, y, z) = x + y’z n Truth Table: Fig. 1 -3(a) n Relationship between a function and variable 2 n Combination Variable n = 3 Computer System Architecture x y z F 0 0 1 1 0 1 0 0 1 1 0 1 0 1 Logic Diagram: Fig. 1 -3(b) Algebraic Expression Logic Diagram(gates로 표현) x y z Chap. 1 Digital Logic Circuits F

1 -3 Boolean Algebra n Purpose of Boolean Algebra u To facilitate the analysis and design of digital circuit n Convenient Tools u Truth table : relationship between binary variables u Logic diagram : input-output relationship u Find simpler circuits for the same function n Boolean Algebra Rule : Tab. 1 -1 - Operation with 0 and 1: x + 0 = x , x + 1 = 1 , x • 1 = x , x • 0 = 0 - Idempotent Law: x + x =x , x • x = x - Complementary Law: x + x' = 1 , x • x' = 0 - Commutative Law: x + y = y + x , x • y = y • x - Associative Law: x + (y + z) = (x + y) + z , x • ( y • z) = (x • y) • z - Distributive Law: x • ( y+ x) = (x • y) + (x • z) , x + (y • z) = (x + y) • (x + z) - De. Morgan's Law: (x + y)' = x' • y’ , (x • y )’ = x’ + y’ General Form: (x 1 + x 2 + x 3 + … xn)' = x 1' • x 2' • x 3' • … xn’ (x 1 • x 2 • x 3 • … xn) ' = x 1' + x 2' + x 3' + … xn’ Computer System Architecture Chap. 1 Digital Logic Circuits 20

1 -3 Boolean Algebra n [예제] u F= AB’ + C’D + AB’ + C’D = x + x (let x= AB’ + C’D) =x = AB’ + C’D Computer System Architecture n [예제] 21 Fig. 1 -6(a) u F= ABC + ABC’ + A’C = AB(C + C’) + A’C Fig. 1 -6(b) = AB + A’C 1 inverter, 1 AND gate 감소 Chap. 1 Digital Logic Circuits

1 -3 Boolean Algebra Computer System Architecture Chap. 1 Digital Logic Circuits 22

23 n Fig. 1 -4 2 graphic symbols for NOR gate x y z (x+y+z)’ x y z (a) OR-invert n x’ y’z’ (b) invert-OR Fig. 1 -5 2 graphic symbols for NAND gate x y z (xyz)’ (a) NAND-invert Computer System Architecture x y z (x’+y’+z’) (b) invert-NAND Chap. 1 Digital Logic Circuits

1 -4 Map Simplification n Karnaugh Map(K-Map) u Map method for simplifying Boolean expressions n Minterm / Maxterm u Minterm : n variables product ( x=1, x’=0) u Maxterm : n variables sum (x=0, x’=1) n 2 variables example n F = x’y + xy m 1 m 0 + m 1 + m 2 + m 3 ( m 1 + m 3 ) (Complement = M 0 Computer System Architecture M 0 M 1 M 2 M 3 M 2 ) Chap. 1 Digital Logic Circuits 24

25 1 -4 Map Simplification n Map u 2 variables u 3 variables B u 4 variables C B A A B A C u 5 variables C D B A E D F Fig 1 -7 Maps for two-, three-, four-, and five-variable functions Computer System Architecture Chap. 1 Digital Logic Circuits

26 1 -4 Map Simplification n [예제] F= x + y’z (1) Truth Table (2) (3) Karnaugh Map y x z F= x + y’z Computer System Architecture Chap. 1 Digital Logic Circuits

1 -4 Map Simplification n Adjacent Square u Number of square = 2 n (2, 4, 8, …. ) u The squares at the extreme ends of the same horizontal row are to be considered adjacent u The same applies to the top and bottom squares of a column u The four corner squares of a map must be considered to be adjacent u Groups of combined adjacent squares may share one or more squares with one or more group Computer System Architecture Chap. 1 Digital Logic Circuits 27

28 1 -4 Map Simplification n [예제] B u F=AC’ + BC n A [예제] u F=C’ + AB’ n C B C C A [예제] u F=B’C’ + B’D’ + A’CD’ B n Product-of-Sums Simplification A D F=B’D’ + B’C’ + A’C’D Sum of product F’=AB + CD + BD’(square marked 0’s) F’’(F)=(A’ + B’)(C’ + D’)(B’ + D) B A Product of Sum Computer System Architecture C Chap. 1 Digital Logic Circuits D

29 1 -4 Map Simplification n NAND Implementation u Sum of Product : F=B’D’ + B’C’ + A’C’D B’ D’ C’ A’ D n NOR Implementation u Product of Sum : F=(A’ + B’)(C’ + D’)(B’ + D) A’ B’ C’ D’ n D’ Don’t care conditions u F(A, B, C)= (0, 2, 6), d(A, B, C)= (1, 3, 5) u F=A’ + BC’= (0, 1, 2, 3, 6) Computer System Architecture Chap. 1 Digital Logic Circuits B 1 A X X X C 1

1 -5 Combinational Circuits n 30 Combinational Circuits u A connected arrangement of logic gates with a set of inputs and outputs n Analysis in Combinational Circuits (Logic Gates) u Logic circuits diagram n . . . i 0 i 1 . . . u Fig. 1 -15 Block diagram of a combinational circuit f 0 f 1 fm Boolean function or Truth table Design(Analysis의 반대) u 1. The Problem is stated Experience u 2. I/O variables are assigned u 3. Truth table(I/O relation) u 4. Simplified Boolean Function(Map 과 Boolean 대수 이용) u 5. Logic circuit diagram Computer System Architecture Chap. 1 Digital Logic Circuits

31 1 -5 Combinational Circuits n Design Example : Half Adder u 1. Half adder is a combinational circuits that forms the arithmetic sume of two input bit u 2. 2 Input(x, y), 2 Output(S: sum, C: carry) u 3. Truth Table u 4. Simplification C= xy u 5. Logic circuit diagram S= x’y + xy’ =x y u 6. Block diagram X S H. A y Computer System Architecture Chap. 1 Digital Logic Circuits C

32 1 -5 Combinational Circuits n Design Example : Full Adder u 1. Full adder is a combinational circuits that forms the arithmetic sume of three input bit(Carry considered) u 2. 3 Input(x, y, z), 2 Output(S: sum, C: carry) u 3. Truth Table u 4. Simplification y y x x z C= xy’z + x’yz + xy =z(xy’ + x’y) + xy =z(x y) + xy u 5. Logic circuit diagram x y c z s Computer System Architecture Chap. 1 Digital Logic Circuits z S=xy’z’ + x’y’z + xyz + x’yz’ = z’(xy’ + x’y) + z(x’y’ + xy) = z’(x y) + z(x y)’ =a’b + ab’ (let a=z, b=x y) =x y z (x y)’=(xy’+x’y)’ =(x’+y)(x+y’) =x’x+x’y’+xy+yy’ =x’y’+xy

1 -5 Combinational Circuits X Y F. A Z Fig 1 -18. Block diagram Computer System Architecture Chap. 1 Digital Logic Circuits S C 33

34 1 -6 Flip-Flops n Combinational Circuit = Gate Sequential Circuit = Gate + F/F Flip-Flop u The storage elements employed in clocked sequential circuit u A binary cell capable of storing one bit of information n SR(Set/Reset) F/F n D(Data) F/F u “no change” condition이 없다 : Q(t+1)=D l n JK(Jack/King) F/F n u JK F/F is a refinement of the SR F/F u The indeterminate condition of the SR type is defined in complement Computer System Architecture 해결방법 : 1) Disable Clock 2) Feedback output into input T(Toggle) F/F u T=1(J=K=1), T=0(J=K=0) 이면 JK F/F u 수식 표현 : Q(t+1)= Q(t) T Chap. 1 Digital Logic Circuits

1 -6 Flip-Flops n SR(Set/Reset) F/F S Q’ n S D CP Q R n R JK(Jack/King) F/F J D(Data) F/F n T(Toggle) F/F T CP K E Computer System Architecture Chap. 1 Digital Logic Circuits 35

36 1 -6 Flip-Flops Positive clock transition n Edge-Triggered F/F u State Change : Clock Pulse l Rising Edge(positive-edge transition) l Falling Edge(negative-edge transition) ts th u Setup time(20 ns) l minimum time that D input must remain at constant value before the transition. u Hold time(5 ns) l minimum time that D input must not change after the positive transition. u Propagation delay(max 50 ns) l time between the clock input and the response in Q l 일반 논리 gate에서는 2 -20 ns이며 setup 및 hold time은 F/F에서만 정의되며 일반 논리 gate에서는 정의되지 않음. u Master-Slave F/F l 2개의 F/F을 사용(Slave 와 Master F/F)하며 negative-edge transition 사용 l 위와 같이 사용하는 이유: Race 현상을 방지 Computer System Architecture Chap. 1 Digital Logic Circuits

37 1 -6 Flip-Flops n D Master – Slave D(Data) F/F D C Master D C Slave Q C a. 논리도 Computer System Architecture b. 파형도 Chap. 1 Digital Logic Circuits

1 -6 Flip-Flops n Race 현상 u 조건 - Setup time > Propagation delay u 증상 - 0 과 1을 반복하다가 Unstable한 상태가 된다 u 해결책 - Edge triggered F/F 또는 Master/Slave F/F 사용 u 예제 l 7470 : J-K Edge triggered F/F l 7471 : J-K Master/Slave F/F n Excitation Table u Required input combinations for a given change of state u Present State 와 Next State로 표현 Don’t Care Computer System Architecture 1 : Set to 1 0 : Complement 1 : Clear to 0 0 : No change Chap. 1 Digital Logic Circuits 38

39 1 -7 Sequential Circuits n n A sequential circuit is an interconnection of F/F and Gate Clocked synchronous sequential circuit Combinational Circuit = Gate Sequential Circuit = Gate + F/F Input Combinational Circuit Output Flip-Flops Clock n Flip-Flop Input Equation u Boolean expression for F/F input u Input Equation 예제 l DA = Ax + Bx, DB = A’x x u Output Equation l y = Ax’ + Bx’ u Fig. 1 -25 Example of a sequential circuit DA A A’ DB Clock B B’ y Computer System Architecture Chap. 1 Digital Logic Circuits

1 -7 Sequential Circuits n State Table n u Present state, input, next state, output 표현 Input Equ. = Next State n State Diagram u Graphical representation of state table l Circle(state), Line(transition), I/O(input/output) Design Example: Binary Counter Next State = Output u x=1: 00, 01, 10, 11, 00, 01, …. . x=0: no change u Excitation Table(2 bit counter = 2 F/F) u State Diagram: 4 state(00, 01, 10, 11) Computer System Architecture 40 Chap. 1 Digital Logic Circuits

41 1 -7 Sequential Circuits u Map for simplification l Input variable: A, B, x u Logic Diagram B B JA 1 X A KA X x X X X 1 A x KA=Bx JA=Bx B B JB 1 1 A JB=x n X X X x X X KB A X X 1 1 X X x KA=x Sequential Circuit Design Procedure u 1 -5 절 참고(Combinational Circuit Design) u Sequential Circuit은 절차 3에서 State diagram 및 State table 이용 u F/F 수: 2 m+n (m - State 수, n - Input 수) Computer System Architecture Chap. 1 Digital Logic Circuits 1. The Problem is stated 2. I/O variables are assigned 3. Truth table(I/O relation) 4. Simplified Boolean Function 5. Logic circuit diagram