Wir schaffen Wissen heute fr morgen Paul Scherrer

Wir schaffen Wissen – heute für morgen Paul Scherrer Institut Ernst Johansen The „Pie in the Sky“ PSI, 11. März 2010

Agenda Unified Processing Architecture Motivation Technology Feasibility Proposal Cost Discussion PSI, 11. März 2010

Motivation PSI Motivation • We will soon operate four Machines (2 x proton, 2 x electron) • Maintenance will become a huge Challenge • Focus on synergies between all machines • We need very long lifetime for the control solutions Personal Motivation • Bring in +15 years of experience in designing Industrial Control Systems • I like do design systems on a “decent” platform PSI, 11. März 2010

Strategy Vision Take initiative to get into win-win situations Proposed Strategy We should develop a common embedded control framework, reusable for all of our digital control applications. This framework should be designed for long lifetime and be based on reuse. Don’t reinvent the wheel… Pre-study results… PSI, 11. März 2010

Potential for Cost Reductions Cooperate with Industry to find a Common Platform Sell Platform into different Markets Swiss. FEL RF Applications PSI IOx. OS PECTRON Process Automation PSI, 11. März 2010

Unified Processing Architecture ? Use Cases PLC Siemens, Rockwell, Wago, Beckhoff IOC VPC GPAC SLS, HIPA PPC, Intel Vx. Works, Linux PPC 405, DSP No OS, Xilkernel PPC 440 DSP, u. C 1. One Architecture 1. One Arch. 2. Higher Rel (ECC) 2. Synergies RF 2. Higher Performance 2. Retrofit 3. Lower cost (SW) 3. Lower eng. cost 3. Compatibility UPA Common CPU, OS Common FW PSI, 11. März 2010

Platforms Religion…. They somehow do it all… don’t they ? Its very expensive to change them You need alliances to be strong… Technology Are there any new technologies around ? How to apply these to different platforms ? Significant Improvement PCI Express (FMC) How to apply PCI Express to VME 64 x ? PSI, 11. März 2010

Design – VME Bottleneck CPU VME 64 x ≈250 MB/s (2 Gbps) FPGA PSI, 11. März 2010

VME 64 x Card Design – Additional Bandwidth at Low-Cost GEthernet 2 x 2 Gbps Duplex CPU PCIe 4 x 8 Gbps Duplex FPGA SFP 4 x 15 Gbps Duplex PSI, 11. März 2010

Design – Scalable Bandwidth COTS 10 G Ethernet Switch N x 2 Gbps CPU CPU N x 8 Gbps FPGA N x 15 Gbps PCI Express, Fiber Optics N = 1. . 21 PSI, 11. März 2010

Improved P 0 – VME 64 x Compatible Improved P 0 • 2 mm Legacy Compatible • High-Speed Links • SFP 7 Gbps SPF PCIe Versa. Link PSI, 11. März 2010

VITA 57. 1 -2008 FMC – High-Speed I/O Defined PSI standard, but… VITA 57. 1 -2008 FPGA Mezzanine Cards is here • Supports the PSI Use Cases • Broad industrial acceptance • 69 x 76. 5 mm 2 (small) Examples • 4 DSP – 8 channel ADC 250 Msps @ 14 -bit – 4 channel ADC 125 Msps @ 16 -bit – 1 channel ADC 5 Gsps @ 8 -bit – 4 channel DAC 1000 Msps @ 16 -bit • Curtiss-Wright – 4 channel DAC 500 Msps @ 16 -bit Proposal • VITA 57. 1 -2008 compatibility • Support for extended PCB size where required PSI, 11. März 2010

Ether. CAT – Medium-Speed I/O Bus Master • Based on standard Ethernet • Very low protocol overhead Key Data • Performance – – – 256 Digital-I/Os in 12 µs 1. 000 Digital-I/Os in 30 µs 200 Analog-I/Os (16 Bit) in 50 µs 100 Servo-axis in 100 µs 12. 000 Digital-I/Os in 350 µs Suitable PCI / PMC replacement • Suitable IP-module replacement • Technology • http: //www. beckhoff. de PSI, 11. März 2010

Hardware Design Are there any reusable existing products on the market? What has to be extended ? IOx. OS TOSCA II Design Kit • Designed for Reuse • Based on high quality TOSCA product: VME 64 x - PCIe Bridge • Supports cost efficient Xilinx Virtex-6 CXT • Architecture PCIexpress 2. 0 non-blocking Switch • High performance VME 64 x interface • VHDL Simulation Framework • Linux Drivers and Test Framework • Excellent documentation • All VHDL source and hardware design files available !! Dual Core CPU Extensions • High-Rel CPU with ECC on memory (Atom has not ECC) • Long term availability - Freescale • Low power 45 nm process PSI, 11. März 2010

TOSCA II HW+FW reuse P 2020 RDS reuse Unified Processing Architecture – IOx. OS PSI, 11. März 2010

Unified Processing Architecture – HW Benefits High-Reliability Dual Core IOC ≈250 USD Ethernet Remote debugging & download FMC (Digitizers) XMC (PCIe) PMC (PCI) compatible Large and fast FPGA ≈300 USD Fast VME 64 x ≈100 USD Electrical PCI Express (P 0) High-End Workstation PSI, 11. März 2010

IOx. OS Thermal Design PMC / XMC / FMC Cooler Rear IO PMC / XMC / FMC PSI, 11. März 2010

Software Design Are there any existing products on the market ? What has to be extended ? IOx. OS TOSCA II • Linux Drivers and Test Framework P 2020 RDS • Linux BSP Co. De. Sys • High-Performance soft PLC with Ether. CAT Stack • Linux PREEMPT_RT Open Source Real Time • Linux PREEMPT_RT patch • SMP up to 10 k. Hz, AMP >10 k. Hz EPICS • Linux Port PSI, 11. März 2010

Linux on P 2020 - Capabilities Similar to Emerson MVME 4100 performance, but has additional • Second CPU core for real-time DSP Real-Time PREEMPT_RT on P 2020 in SMP-Mode (One operating system – two cores) • Patch is easy to apply and well supported • Moved all Processes to PPC 0 • Moved all Interrupts to PPC 0 • 100% PPC 0 load (cyclictest) • Executed EPICS on PPC 0 • Executed cylictest on PPC 1 Results • Min 5 us Avg 5 us 40 us Conclusions Guarding one CPU enables hard real-time behavior running EPICS in parallel Preliminary results shows that 10 k. Hz @ 50% CPU load is feasible. PSI, 11. März 2010

Unified Processing Architecture – Software/Firmware UPA Rear I/O EPICS Ethernet EPICS IOC Matlab M C SFP Timing Shared Mem Ether. CAT I/O Motion ≈300 USD Co. De. Sys Ether. CAT (EPICS) PCIe switch PCIe Workstation Shared Mem FMC IOx. OS TOSCA II Versa. Link Power Units Interlock RF PSI, 11. März 2010

IOx. OS - Design Partner IOx. OS • Swiss Company Gland by Geneva • Experts VME, PCIe, Board Design Products • VME-PCIe • TOSCA High-Performance Bridge Switch Fabric Status • NDA • Offer • Sell Signed Design UPA Into research community PSI, 11. März 2010

PECTRON – Power Electronics Control Status • Swiss start-up company • Share NRE • Sell into Power Electronic Market Crate • ELMA 2 -Slots PLC • Co. De. Sys Soft. PLC • IEC 61131 -3 Programming Ether. CAT • Beckhoff PSI, 11. März 2010

3 S - Co. De. Sys SP V 3 (OEM) IEC 61131 -3 • De-facto Industrial Standard • Used by several hundred companies • Free Download • Supports all IEC 61131 -3 Languages • Easy to learn • Fast engineering • Runtime engine is licensed Status • Offer Porting to UPA PSI, 11. März 2010

VITA 57. 1 -2008 FMC – Partner Strategy • Cooperate with Industry • Utilize latest available technology Curtiss-Wright • NDA • Next Generation FMC • ADC 250 Msps @ 16 -bit ? ? ? 4 DSP • Next Generation FMC • 6 -channel ADC 250 Msps @ 16 -bit ? ? ? PSI, 11. März 2010

Conclusions We need a long term strategy for our control systems UPA enables one single framework for PLC, IOC , Medium-Speed- and RF applications VME 64 x is the most stable specification and compatible with SLS and HIPA Retrofit Higher integration we can considerably reduce the cost of VME 64 x The UPA has low component count and ECC – suitable for high-reliability applications With UPA we can achieve near to zero long-term royalties With strategic sourcing a lifetime of 20 years is feasible (if we want to) We get complete design in source code – including hardware and VHDL!!! There are potential partners to get into a win-win situation!!! PSI, 11. März 2010

The „Pie in the Sky“ PSI, 11. März 2010