RISC CISC Architectures Performance comparison assuming similar HW
![RISC / CISC Architectures’ Performance comparison assuming similar H/W Organization Qiuhua Cao William Greenwell RISC / CISC Architectures’ Performance comparison assuming similar H/W Organization Qiuhua Cao William Greenwell](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-1.jpg)
![Outline n n Differences between RISC / CISC Quantitative performance analysis n n n Outline n n Differences between RISC / CISC Quantitative performance analysis n n n](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-2.jpg)
![What the paper suggest? n RISC has many performance advantages over CISC n n What the paper suggest? n RISC has many performance advantages over CISC n n](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-3.jpg)
![Experimental Framework n Paper looks at MIPS M/2000(from RISC) and VAX 8700(from CISC) -same Experimental Framework n Paper looks at MIPS M/2000(from RISC) and VAX 8700(from CISC) -same](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-4.jpg)
![CPU Pipeline Abstractions MIPS and VAX §MIPS instruction fetch stage matches with VAX microinstruction CPU Pipeline Abstractions MIPS and VAX §MIPS instruction fetch stage matches with VAX microinstruction](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-5.jpg)
![About MIPS and VAX n Strong organizational similarities n n n Ex: CPU Pipeline About MIPS and VAX n Strong organizational similarities n n n Ex: CPU Pipeline](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-6.jpg)
![Spec Benchmarks used We have used 3 integer (in C) benchmarks § Espresso § Spec Benchmarks used We have used 3 integer (in C) benchmarks § Espresso §](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-7.jpg)
![Tools used to generate benchmarks §VAX 8700 §Hardware monitor §Every microinstruction count is kept Tools used to generate benchmarks §VAX 8700 §Hardware monitor §Every microinstruction count is kept](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-8.jpg)
![n Instructions and CPI n Instructions and CPI](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-9.jpg)
![n Instructions and CPI MIPS < VAX n Instructions and CPI MIPS < VAX](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-10.jpg)
![n Instructions and CPI MIPS exe/ VAX exe G mean = 2. 17 n Instructions and CPI MIPS exe/ VAX exe G mean = 2. 17](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-11.jpg)
![n Instructions and CPI VAX CPI/ MIPS CPI G mean = 5. 77 n Instructions and CPI VAX CPI/ MIPS CPI G mean = 5. 77](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-12.jpg)
![n Instructions and CPI Net Effect on Performance cycles per program ratio n Instructions and CPI Net Effect on Performance cycles per program ratio](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-13.jpg)
![n Instructions and CPI SPICE is the best n Instructions and CPI SPICE is the best](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-14.jpg)
![n Three integer compilers Instructions and CPI have biggest RISC Lowest inst ratio n Three integer compilers Instructions and CPI have biggest RISC Lowest inst ratio](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-15.jpg)
![n Instructions and CPI Three lowest RISC three lowest CPI ratio n Instructions and CPI Three lowest RISC three lowest CPI ratio](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-16.jpg)
![n Operation Counts n Operation Counts](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-17.jpg)
![n MIPS per inst < VAX per inst Operation Counts MIPS also equals VAS n MIPS per inst < VAX per inst Operation Counts MIPS also equals VAS](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-18.jpg)
![n Operation Counts MIPS < VAX n Operation Counts MIPS < VAX](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-19.jpg)
![n Operation Counts MIPS mem< VAX mem exception n Operation Counts MIPS mem< VAX mem exception](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-20.jpg)
![n Cache behavior n Cache behavior](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-21.jpg)
![n Cache behavior D highest miss ratio Lowest RISC factor n Cache behavior D highest miss ratio Lowest RISC factor](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-22.jpg)
![n Cache behavior some MIPS > some VAX n Cache behavior some MIPS > some VAX](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-23.jpg)
![MIPS = 2. 66 × VAX MIPS = 2. 66 × VAX](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-24.jpg)
![Case Study n fpppp benchmark n n Highest CPI Ratio, Highest INST Ratio, High Case Study n fpppp benchmark n n Highest CPI Ratio, Highest INST Ratio, High](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-25.jpg)
![Architecture Factors Favoring MIPS n Operand specifier decoding n e. g. Three-register integer add Architecture Factors Favoring MIPS n Operand specifier decoding n e. g. Three-register integer add](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-26.jpg)
![Architecture Factors Favoring MIPS n FP Hardware/Instruction Overlap n n n Data movement between Architecture Factors Favoring MIPS n FP Hardware/Instruction Overlap n n n Data movement between](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-27.jpg)
![Architecture Factors Favoring MIPS n Fancy VAX Instructions n n n Unnecessary functionality and Architecture Factors Favoring MIPS n Fancy VAX Instructions n n n Unnecessary functionality and](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-28.jpg)
![Architecture Factors Favoring MIPS n Translation Buffer n n MIPS has a larger page Architecture Factors Favoring MIPS n Translation Buffer n n MIPS has a larger page](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-29.jpg)
![Architecture Factors Favoring VAX Big I-stream Constants n Not-taken Branches n Architecture Factors Favoring VAX Big I-stream Constants n Not-taken Branches n](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-30.jpg)
![Variance of the RISC Factor n Loose correlation with D-cache misses n Highest RISC Variance of the RISC Factor n Loose correlation with D-cache misses n Highest RISC](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-31.jpg)
![Future of CISC & RISC n VAX may be able to catch up to Future of CISC & RISC n VAX may be able to catch up to](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-32.jpg)
![Summary Table Min Geometric Mean Max VAX CPI 5. 4 9. 9 17. 4 Summary Table Min Geometric Mean Max VAX CPI 5. 4 9. 9 17. 4](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-33.jpg)
![Caveats n n n Compiler influence may skew results. Small sample size with respect Caveats n n n Compiler influence may skew results. Small sample size with respect](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-34.jpg)
- Slides: 34
![RISC CISC Architectures Performance comparison assuming similar HW Organization Qiuhua Cao William Greenwell RISC / CISC Architectures’ Performance comparison assuming similar H/W Organization Qiuhua Cao William Greenwell](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-1.jpg)
RISC / CISC Architectures’ Performance comparison assuming similar H/W Organization Qiuhua Cao William Greenwell Chengdu Huang Kumar Manvendra
![Outline n n Differences between RISC CISC Quantitative performance analysis n n n Outline n n Differences between RISC / CISC Quantitative performance analysis n n n](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-2.jpg)
Outline n n Differences between RISC / CISC Quantitative performance analysis n n n Number of Instructions Cache Behaviour Case study of one(two ? ? ) benchmarks(fp behaviour) Factors favoring RISC , CISC Critique / Conclusion
![What the paper suggest n RISC has many performance advantages over CISC n n What the paper suggest? n RISC has many performance advantages over CISC n n](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-3.jpg)
What the paper suggest? n RISC has many performance advantages over CISC n n n Single cycle L/S instruction (faster, low overhead) Hardwired control ; vastly reduced chip complexity more registers/less MEM references Fixed INST format, fewer instructions MEM accesses are not tightly bound to INSTS
![Experimental Framework n Paper looks at MIPS M2000from RISC and VAX 8700from CISC same Experimental Framework n Paper looks at MIPS M/2000(from RISC) and VAX 8700(from CISC) -same](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-4.jpg)
Experimental Framework n Paper looks at MIPS M/2000(from RISC) and VAX 8700(from CISC) -same underlying organization n Most recent compilers were used for each of the two machines Cycle time determined through machine independent features but its same Spec 1 Release benchmarks used
![CPU Pipeline Abstractions MIPS and VAX MIPS instruction fetch stage matches with VAX microinstruction CPU Pipeline Abstractions MIPS and VAX §MIPS instruction fetch stage matches with VAX microinstruction](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-5.jpg)
CPU Pipeline Abstractions MIPS and VAX §MIPS instruction fetch stage matches with VAX microinstruction fetch stage §Large set of general purpose registers §Single cycle instructions §Delayed branches
![About MIPS and VAX n Strong organizational similarities n n n Ex CPU Pipeline About MIPS and VAX n Strong organizational similarities n n n Ex: CPU Pipeline](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-6.jpg)
About MIPS and VAX n Strong organizational similarities n n n Ex: CPU Pipeline abstractions match up closely VAX Microinstruction stage features a lot of RISC features MIPS has split I-Cache and D-Cache unlike VAX which has same I+D Cache MIPS has larger page size Same Cycle time -- A COINCIDENCE ? ? MIPS has much faster MEM access , FP ops
![Spec Benchmarks used We have used 3 integer in C benchmarks Espresso Spec Benchmarks used We have used 3 integer (in C) benchmarks § Espresso §](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-7.jpg)
Spec Benchmarks used We have used 3 integer (in C) benchmarks § Espresso § Eqntott § Li Compiled using VAX Cv 3. 1 , CCv 2. 0 § And 7 floating point (in fortran )benchmarks § § § Spice 2 g 6 Matrix 300 Nasa 7 Fpppp Tomcatv doduc Compiled using VAX Fortran V 5. 0 -1 , MIPS f 77 v 2. 0
![Tools used to generate benchmarks VAX 8700 Hardware monitor Every microinstruction count is kept Tools used to generate benchmarks §VAX 8700 §Hardware monitor §Every microinstruction count is kept](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-8.jpg)
Tools used to generate benchmarks §VAX 8700 §Hardware monitor §Every microinstruction count is kept §Data / instruction accesses can be studied §MIPS M/2000 §Pixie/pixstats §Division into basic blocks and counting instruction in each basic blocks
![n Instructions and CPI n Instructions and CPI](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-9.jpg)
n Instructions and CPI
![n Instructions and CPI MIPS VAX n Instructions and CPI MIPS < VAX](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-10.jpg)
n Instructions and CPI MIPS < VAX
![n Instructions and CPI MIPS exe VAX exe G mean 2 17 n Instructions and CPI MIPS exe/ VAX exe G mean = 2. 17](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-11.jpg)
n Instructions and CPI MIPS exe/ VAX exe G mean = 2. 17
![n Instructions and CPI VAX CPI MIPS CPI G mean 5 77 n Instructions and CPI VAX CPI/ MIPS CPI G mean = 5. 77](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-12.jpg)
n Instructions and CPI VAX CPI/ MIPS CPI G mean = 5. 77
![n Instructions and CPI Net Effect on Performance cycles per program ratio n Instructions and CPI Net Effect on Performance cycles per program ratio](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-13.jpg)
n Instructions and CPI Net Effect on Performance cycles per program ratio
![n Instructions and CPI SPICE is the best n Instructions and CPI SPICE is the best](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-14.jpg)
n Instructions and CPI SPICE is the best
![n Three integer compilers Instructions and CPI have biggest RISC Lowest inst ratio n Three integer compilers Instructions and CPI have biggest RISC Lowest inst ratio](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-15.jpg)
n Three integer compilers Instructions and CPI have biggest RISC Lowest inst ratio
![n Instructions and CPI Three lowest RISC three lowest CPI ratio n Instructions and CPI Three lowest RISC three lowest CPI ratio](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-16.jpg)
n Instructions and CPI Three lowest RISC three lowest CPI ratio
![n Operation Counts n Operation Counts](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-17.jpg)
n Operation Counts
![n MIPS per inst VAX per inst Operation Counts MIPS also equals VAS n MIPS per inst < VAX per inst Operation Counts MIPS also equals VAS](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-18.jpg)
n MIPS per inst < VAX per inst Operation Counts MIPS also equals VAS count
![n Operation Counts MIPS VAX n Operation Counts MIPS < VAX](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-19.jpg)
n Operation Counts MIPS < VAX
![n Operation Counts MIPS mem VAX mem exception n Operation Counts MIPS mem< VAX mem exception](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-20.jpg)
n Operation Counts MIPS mem< VAX mem exception
![n Cache behavior n Cache behavior](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-21.jpg)
n Cache behavior
![n Cache behavior D highest miss ratio Lowest RISC factor n Cache behavior D highest miss ratio Lowest RISC factor](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-22.jpg)
n Cache behavior D highest miss ratio Lowest RISC factor
![n Cache behavior some MIPS some VAX n Cache behavior some MIPS > some VAX](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-23.jpg)
n Cache behavior some MIPS > some VAX
![MIPS 2 66 VAX MIPS = 2. 66 × VAX](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-24.jpg)
MIPS = 2. 66 × VAX
![Case Study n fpppp benchmark n n Highest CPI Ratio Highest INST Ratio High Case Study n fpppp benchmark n n Highest CPI Ratio, Highest INST Ratio, High](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-25.jpg)
Case Study n fpppp benchmark n n Highest CPI Ratio, Highest INST Ratio, High RISC factor High number of FP L/S ops on MIPS; High density of double precision operand specifiers on VAX MIPS has fast FP operations VAX has no instruction overlapping
![Architecture Factors Favoring MIPS n Operand specifier decoding n e g Threeregister integer add Architecture Factors Favoring MIPS n Operand specifier decoding n e. g. Three-register integer add](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-26.jpg)
Architecture Factors Favoring MIPS n Operand specifier decoding n e. g. Three-register integer add n n VAX: 4 cycles ; MIPS: 1 cycle Number of Registers n n VAX: 15 32 -bit general regs MIPS: 32 32 -bit general regs and 16 64 -bit FP regs
![Architecture Factors Favoring MIPS n FP HardwareInstruction Overlap n n n Data movement between Architecture Factors Favoring MIPS n FP Hardware/Instruction Overlap n n n Data movement between](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-27.jpg)
Architecture Factors Favoring MIPS n FP Hardware/Instruction Overlap n n n Data movement between chips MIPS has register destination FP ops only Simple Jump/branches n VAX Condition codes
![Architecture Factors Favoring MIPS n Fancy VAX Instructions n n n Unnecessary functionality and Architecture Factors Favoring MIPS n Fancy VAX Instructions n n n Unnecessary functionality and](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-28.jpg)
Architecture Factors Favoring MIPS n Fancy VAX Instructions n n n Unnecessary functionality and unnecessary overhead e. g. VAX procedure call and return inst Instruction Scheduling n MIPS can fill delay slots
![Architecture Factors Favoring MIPS n Translation Buffer n n MIPS has a larger page Architecture Factors Favoring MIPS n Translation Buffer n n MIPS has a larger page](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-29.jpg)
Architecture Factors Favoring MIPS n Translation Buffer n n MIPS has a larger page size Branch Displacement Size n n VAX: 8 bits MIPS: 16 bits
![Architecture Factors Favoring VAX Big Istream Constants n Nottaken Branches n Architecture Factors Favoring VAX Big I-stream Constants n Not-taken Branches n](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-30.jpg)
Architecture Factors Favoring VAX Big I-stream Constants n Not-taken Branches n
![Variance of the RISC Factor n Loose correlation with Dcache misses n Highest RISC Variance of the RISC Factor n Loose correlation with D-cache misses n Highest RISC](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-31.jpg)
Variance of the RISC Factor n Loose correlation with D-cache misses n Highest RISC factor: li n n Lowest D-cache miss ratio Lots of function call overhead for VAX Address unaligned mem refs for VAX Lowest RISC factor: spice
![Future of CISC RISC n VAX may be able to catch up to Future of CISC & RISC n VAX may be able to catch up to](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-32.jpg)
Future of CISC & RISC n VAX may be able to catch up to current RISC architectures. n n n Figure 4 from paper RISC will incorporate advanced implementation techniques. VAX will always play “catch up. ”
![Summary Table Min Geometric Mean Max VAX CPI 5 4 9 9 17 4 Summary Table Min Geometric Mean Max VAX CPI 5. 4 9. 9 17. 4](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-33.jpg)
Summary Table Min Geometric Mean Max VAX CPI 5. 4 9. 9 17. 4 MIPS CPI 1. 1 1. 7 3. 1 CPI Ratio 3. 5 5. 8 10. 4 Inst. Ratio 1. 1 2. 2 3. 9 RISC-F 1. 8 2. 7 3. 7 Source: Bhandarkar & Clark. “Performance from
![Caveats n n n Compiler influence may skew results Small sample size with respect Caveats n n n Compiler influence may skew results. Small sample size with respect](https://slidetodoc.com/presentation_image_h/1e2b648b9f50588b131cef3720c14c12/image-34.jpg)
Caveats n n n Compiler influence may skew results. Small sample size with respect to benchmark programs Application-level vs. system-level comparison n Effect of operating system primitives
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