Oscillation Control in CMOS PhaseLocked Loops A Thesis

Oscillation Control in CMOS Phase-Locked Loops A Thesis Presented to The Academic Faculty by Bortecene Terlemez Ph. D Candidate in School of ECE 11/04/2004 Dr. Martin Brooke, Advisor Georgia Institute of Technology School of Electrical and Computer Engineering Microelectronics Research Center Atlanta, GA 30332 -0269 1

Outline § PLL history and fundamentals § PLL Architectures § Oscillation control in CMOS charge-pump PLLs § Single-ended control for multi-GHz charge-pump PLLs § Design of a low-noise 1. 8 GHz charge-pump PLL § Design of a low-noise 5. 8 GHz charge-pump PLL § Differential control for multi-GHz charge-pump PLLs § Performance comparison § Pulse-stream coded PLLs § Summary/Conclusions/Contributions 2

Brief Phase-Locked Loop (PLL) History § 1932: Invention of “coherent communication” (de. Bellescize) § 1943: Horizontal and vertical sweep synchronization in television (Wendt and Faraday) § 1954: Color television (Richman) § 1965: PLL on integrated circuit § 1970: Classical digital PLL § 1972: All-digital PLL § PLLs today: in every cell phone, TV, radio, pager, computer, … § § § Clock and Data Recovery Frequency Synthesis Clock Generation Clock-skew minimization Duty-cycle enhancement 3

Phase-Locked Loop § Phase Detector (PD): This is a nonlinear device whose output contains the phase difference between the two oscillating input signals. § Voltage Controlled Oscillator (VCO): This is another nonlinear device which produces an oscillation whose frequency is controlled by a lower frequency input voltage. § Loop Filter (LF or LPF): While this can be omitted, it is always conceptually there since PLLs depend on some sort of low pass filtering in order to function properly § A feedback interconnection: Namely the phase detector takes as its input the reference signal and the output of the VCO. The output of the PD, the phase error, 4 is used as the control voltage for the VCO.

PLL Architectures 5

PLL Architectures – Linear PLL vs Digital PLL § No frequency tracking § Input amplitude dependency § Nonlinear phase detector gain § No frequency tracking § Duty-cycle sensitivity (can be solved by edge triggered phase detector 6

PLL Architectures – All-digital PLL § Lower sensitivity to digital -switching noise § Easier to transfer a design between technologies § Faster lock-in times § Higher complexity § Bigger die size § No true frequency synthesis (in general) 7

PLL Architectures - Charge Pump PLL § Stability: Two poles at the origin § Zero in LPF § Auxiliary charge pump § Zero phase error (ideally) § Unlimited capture range (ideally) 8

Oscillation Control in Charge Pump PLLs § Charge Pump PLL: contemporary applications § PFD and charge pump nonidealitites: 45% of the output phase jitter 1 § Phase-Frequency Detector § Possible dead zone § Possible duty-cycle dependency § Clock skew in Clock/Data § Possible unbalanced output generation Recovery § Reference spur in § Charge Pump Frequency Synthesis § Possible current asymmetry § Possible current leakage 1 V. Kaenel, D. Aebicher, C. Piguet, and E. Dijkstra, “A 320 MHz 1. 5 m. W @ 1. 35 V CMOS PLL for microprocessor clock generation, ” in Journal of Solid-State Circuits, Vol. 31, No. 11, Nov. 1996. 9

Phase-Frequency Detector - Behavior § Three-state device § PLL capture range § Maximum operating frequency: orthogonal inputs § Reset pulse § Too short = dead zone § Too wide = VCO control perturbation 10

Charge Pump - Behavior § Iup: charging current § Idn: discharging current § S 1, S 2: switches Effective charge pump requirements: § Equal charge/discharge current at any CP output voltage § Minimal charge-injection and feed-through (due to switching) at the output node § Minimal charge sharing between the output node and any floating node, i. e. MOS switches at off position 11

Single-ended control for multi-GHz charge-pump PLLs Design of a low-noise 1. 8 GHz charge-pump PLL 12

Phase-Frequency Detector - Design § 0. 18μ TSMC CMOS § Differential outputs § Reset pulse = 0. 2 ns VDD=1. 8 V § Maximum frequency ≈ 600 MHz § Significant power dissipation above 100 MHz 13

Single-Ended Charge Pump – Design Replica Biasing § No charge sharing § No charge injection 14

Differential VCO with Single-Ended Control Saturated Gain Stage with Regenerative Elements § Delay control by varying latch strength § Two sets of inputs for multiple-pass architecture § Tuning range control by varying M 3 and M 4 sizing Delay Stage : C. H. Park, and B. Kim, “A Low-Noise, 900 -MHz VCO in 0. 6 - m CMOS, ” IEEE J. Solid State Circuits, vol. 34, pp. 586 -591, May 1999. 15

Differential VCO with Single-Ended Control 9 -Stage Multiple-Pass Loop § Auxiliary loops nested inside main loop § Frequency Improvement § Effective stage delay reduced § Noise Improvement § Slew rate increased 16

Differential VCO with Single-Ended Control Testing Issues § Current-mode logic dividers: 1/2 to 1/64 of actual frequency § Current-mode logic buffers § DTOS: Differential to single-ended conversion § Driver chain § Turn-off circuitry to reduce cross-talk 17

Differential VCO with Single-Ended Control Layout 18

Differential VCO with Single-Ended Control Simulation vs Measurement § VCO Range § Simulation: 1. 16 – 1. 93 GHz § Measurement: 1. 10 – 1. 86 GHz 19

1. 8 GHz Low-Noise PLL Measurement Summary PLL with 9 -stage ring VCO Range (MHz) Lock-in Range (MHz) 124. 4 – 128. 5 Internal Freq. (MHz) 1180 - 1840 Division Ratio 16 VCO Gain (MHz/V) 770 ICP (μA) 100 Open-Loop Phase Margin 81 Closed-Loop BW (KHz) § Off-chip LPF: flexibility in testing 1120 - 1860 625. 5 RMS jitter (ps) 1. 7 Phase Noise (-d. Bc/Hz) 116 20

Single-ended control for multi-GHz charge-pump PLLs Design of a low-noise charge-pump PLL for maximum frequency 21

Differential VCO with Single-Ended Control 3 -Stage Multiple-Pass Loop § VCO Range § Simulation: 5. 18 – 6. 11 GHz § Measurement: 5. 35 – 6. 11 GHz 22

Differential VCO with Single-Ended Control Phase Noise for the 3 -Stage Multiple-Pass Loop Measurement Power Spectrum at ¼ Output of the 3 -Stage Ring § § Simulation: Spectre. RF Power Spectrum at 5. 79 GHz center frequency Simulation: -99. 5 d. Bc/Hz @ 1 MHz offset from ~6 GHz central frequency Measurement: -99. 4 d. Bc/Hz @ 1 MHz offset from ~6 GHz central frequency 23

5. 8 GHz Low-Noise PLL Measurement Summary PLL with 3 -stage ring VCO Range (MHz) 51620 - 5930 Lock-in Range (MHz) 166 - 182. 5 Internal Freq. (MHz) 5310 – 5840 Division Ratio 32 VCO Gain (MHz/V) 793 ICP (μA) 100 Open-Loop Phase Margin 73. 4 Closed-Loop BW (KHz) 248. 4 RMS jitter (ps) 2. 6 Phase Noise (-d. Bc/Hz) 110 24

Differential control for multi-GHz charge-pump PLLs 25

Differential Charge Pump – Design § Output linear range (0. 315 V, 1. 390 V) § Differential outputs: FST and SLW 26

Charge Pump – Common-Mode Feedback (CMFB) § § Sampled data CMFB transconductance gain: 40µA/V CMFB bandwidth: 3 KHz CMFB phase-margin: 76º 100µA § Capacitors § DC voltage stability § Diodes § No effect on operation § Discharging metal during the etching process 27

Charge Pump - Layout 150 x 130 µm 2 28

Charge Pump – Post Layout Simulation § High output resistance § No charge sharing § Decreased charge injection 29

Differentially Controlled LC Oscillator - I Accumulation mode MOS varactor § Differential fine tuning: Accumulation mode MOS varactors § Digital coarse tuning: Mi. M capacitors § Three-turn inductor § 2. 4 n. H, 1. 7 mm, Q~9. 5 § Thick top metal § Frequency goal: 2. 5 GHz 30

Differentially Controlled LC Oscillator - II 1/16 output fo = 157. 8 MHz PN@100 KHz = -83. 8 d. Bc/Hz 31

PLL – Test Setup § Stable nested loops § CMFB BW ≈3 KHz ≈200 KHz << 2. 5 GHz PLL with LC VCO << Loop BW Reference ≈150 MHz Output lock-in range (MHz) 2402 -2518 Input lock-in range (MHz) 150. 1 -157. 4 Division ratio 16 C 1 (n. F) 10 C 2 (p. F) 50 C 3 (p. F) 50 R 1 (Ω) 680 R 2 (Ω) 1500 Phase margin 54. 92 PLL bandwidth (k. Hz) 194. 36 Output RMS jitter (ps) 3. 5 Phase noise @ 1 MHz offset (-d. Bc/Hz) 123 32

PLL - Measurement § Phase lock @ 2. 5 GHz internal frequency § Phase Noise @ 1 MHz offset from 2. 5 GHz: as low as – 123 d. Bc/Hz Reference ½ Output 33

Prototype Chip in 0. 18μm TSMC CMOS § Analog Layout Techniques § § Routing § § Matched and short busses Decoupled parallel analog and digital lines Complimentary digital signals crossing analog buses Power § § § Common centroid topology Stacked parts with dummy components Guard rings Analog and digital supplies merging as close to the pad as possible Wide supply busses at the top metal Pads § Electrostatic discharge protection within the custom designed analog I/O pads 34

PLL Performance Comparison 35

Single-Ended vs Differential Control § For a given frequency range Vdd KVCO § Increased KVCO causes a higher sensitivity to the control line perturbation § For Vctrl = Vmcosωmt § Differential Control Line § Doubles Dynamic Range to drop the spur level by 50% § Common mode rejection lowers the spur levels 36

PLL Measurement Summary PLL at 1. 8 GHz PLL at 5. 8 GHz PLL at 2. 5 GHz single-ended differential 9 -stage multi-pass ring 3 -stage multi-pass ring LC VCO range (MHz) 1120 -1860 5160 -5930 2392 -2525 Output lock-in range (MHz) 1180 -1840 5310 -5840 2402 -2518 74 -115 166 -182. 5 150. 1 -157. 4 VCO gain (MHz/V) 770 793 68 Division ratio 16 32 16 11. 14 C 1 (n. F) 10 10 10 C 2 (p. F) 50 50 50 C 3 (p. F) 50 50 50 R 1 (Ω) 680 680 R 2 (Ω) 1500 Phase margin 68. 66 73. 38 54. 92 PLL bandwidth (k. Hz) 529. 58 248. 37 194. 36 Output RMS jitter (ps) 1. 7 2. 6 3. 5 Phase noise @ 1 MHz offset (-d. Bc/Hz) 116 110 123 Power (m. W) 112 50 5 Control path VCO type Input lock-in range (MHz) Charge-pump gain (μA/rad) 37

PLL Performance Comparison - I Maximum frequencies of published PLLs Phase noise versus maximum frequency 38

PLL Performance Comparison - II Reported output jitter vs measured jitter Reported normalized jitter vs measured jitter 39

Clean vs Noisy Supply Voltage PLL Type Oscillation control path § Increase in jitter RMS phase jitter (ps) clean supply voltage noisy supply voltage 1. 8 GHz single-ended 1. 7 60 5. 8 GHz single-ended 2. 6 50 2. 5 GHz differential 3. 5 20 Periodic cycle-to-cycle jitter in noisy environment: significance of the control line noise § Single-ended: 20 -35 times § Differential: 6 times 40

Control Line Noise Reduction 41

PLL Phase Noise Improvement - I § ↑ Temperature → ↑ Leakage ≡ Loss of lock at low frequencies § Solution: Multiple reset pulses in lock: up’, dn’ § Solution: Adaptive multiple pulses in lock: up’’, dn’’ 42

PLL Phase Noise Improvement - II Static Phase Error Improvement § Best case phase skew for § ICP = 70 µA § ILEAKAGE = 0. 01 ICP § ICP modulation by CMFB: up to 30µA 43

PLL Phase Noise Improvement - III § M=8 § ~6 d. B improved output spur level § M = 32 § ~20 d. B improved output spur level 44

Oscillation Control Summary in Charge Pump PLL § § § Periodical disturbance of the VCO control line Process, voltage, and temperature (PVT) variations of the LPF components Large area consumption by LPF components Limited acquisition time Analog control drawbacks determined by CMOS trends § Reduced linear range (decreasing supply voltage) § Significant leakage and weak-inversion currents (decreasing feature size) § Power supply and substrate noise (increasing integrity) 45

Digital Control and Analog Oscillator § § § Immune to current leakage Precision in Immune to supply/substrate noise oscillation control Tolerant to process variations Semi-custom loop design Monitoring of the internal loop states Quantization noise introduced by the DAC 46

Pulse-Stream Coded Phase-Locked Loop 47

Pulse-Stream Coded Phase-Locked Loop A novel method to render digital control: Phase/frequency comparison coded by pulse trains Dual Pulse-Stream PFD: REF VCO DIR DN UP Single Pulse-Stream PFD: MOD VCO Leads In Phase VCO Lags 48

A Simplified Pulse-Stream Coded PLL Prototype Single Pulse-Stream PFD: § 0. 18μ TSMC CMOS § Highly parameterized for testing basic characteristics § 3 -stage current-controlled oscillator § Active load differential pair stages § 4 -bit shift register 49

A Simplified Pulse-Stream Coded PLL Prototype Control Signals: § § Control 1: pulse width (1 -1. 6 ns) Control 2, 3: delay (0. 2 -1. 5 ns) Control 4: DAC step current Control 5: CCO bias (100 -200 MHz) 50

A Simplified Pulse-Stream Coded PLL Prototype § Control line characteristic § Frequency modulated reference § VCO lagging= current increase § VCO leading= current decrease Simplified psc-PLL: § Slow frequency tracking § Equally weighted control word § No phase lock due to very low resolution § Low number of bits § Equally weighted control word 51

Next Generation Pulse-Stream Coded PLL 52

Next Generation Pulse-Stream Coded PLL § Monotonic binarily-weighted DAC and Counter § Faster capture § Higher resolution § Larger area Quantization noise: § CCO gain= 100 KHz/μA § Tuning range= 100 MHz 53

Single-Pulse Train PFD - Behavior MODIFY output Discrete Characteristic Overall (MODIFY + DIRECTION) Response 54

Single-Pulse Train PFD - Implementation spt. PFD 1 spt. PFD 2 spt. PFD 3 Gated oscillator § § Dead zone is a random variable Pulldown strength § Low: big dead zone § High: noise sensitive operation Low dead zone (80 ps) High power dissipation in lock (1. 4 m. W) § § Low dead zone when output negative edge is utilized (70 ps) Low power dissipation in lock (20μW) tdead-zone, min < tdz < tdead-zone, min + Tclk (1 -duty cycle) 55

Truncated UP/DOWN Counter - Implementation Worst case propagation delay for 8 -bit UP/DN counter § Manchester-like carry look ahead adder Counter Length (bits) Minimum TCLK (ps) 4 570 5 700 8 1200 56

DAC and CCO - Implementation § After continuous time VCO characterization, number of bits can be determined by: 57

Pulse-Stream Coded PLL - Stability F(z): digital filter m: number of short pulses that would fit within a reference period T Root-locus plot for F(z) = 1/ (1 - z-1) UNSTABLE Root-locus plot for F(z) = (1 – 0. 5 z-1)/ (1 - z-1) STABLE FOR 58

Pulse-Stream Coded PLL – Control Line at Lock 59

PLL Design Procedure 60

Conclusions § Basics of PLL operation were shown in a unique control centric flow § Single-ended CPPLLs with ring VCOs were designed and tested for low-noise multi-GHz applications that previously required CPPLLs with LC-VCOs § Design of a low-noise 1. 8 GHz CPPLL § Design of a low-noise 5. 8 GHz CPPLL § An exceptionally performing differential CPPLL was implemented with a unique charge pump and a unique CMFB scheme § Physical design considerations were summarized for low-jitter PLLs § The significance of the control line noise at lower frequencies was addressed along with possible solutions § A novel method for digitizing the control line was described: Pulse-Stream Coded PLL 61

Future Research § Limits of a single-ended PLL design when used along with a voltage regulator § The differential control with the unique CMFB scheme can be utilized to drive higher-Q oscillators to note top-notch measurements § The control line noise reduction techniques can be further studied along with various test structures § Pulse-stream coded PLLs can be considered in dual-loop PLLs as coarse-tuning blocks 62

Questions 63