MICROPROCESSOR THEORY AND INTERFACING Week3 RECAP Interrupts Mechanism

MICROPROCESSOR THEORY AND INTERFACING Week-3

RECAP

Interrupts • Mechanism by which other modules (e. g. I/O) may interrupt normal sequence of processing Provided a way to improve processing efficiency e. g. most external devices are much slower than processor, causes a very wasteful use of resources (after each write op, processor must pause and remain idle until printer catches up)

Interrupts Hardware interrupts: • An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the processor. • If the interrupt is accepted then the processor executes an interrupt service routine. The 8085 has five hardware interrupts (1) (2) (3) (4) (5) TRAP RST 7. 5 RST 6. 5 RST 5. 5 INTR

TRAP: Non-mask able interrupt Unaffected by any mask or interrupt enable Highest priority and vectored interrupt. TRAP interrupt is edge and level triggered (means that the TRAP must go high and remain high until it is acknowledged) • The signal, which overrides the TRAP, is HOLD signal. (i. e. , If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized) Ways to clear TRAP interrupt: 1. By resetting microprocessor (External signal) • •

RST 7. 5: • Mask able interrupt • second highest priority • It is edge sensitive. i. e. Input goes to high and no need to maintain high state until it recognized. Ways to disable interrupt: 1. DI instruction 2. System or processor reset 3. After reorganization of interrupt • Enabled by EI instruction

RST 6. 5 and 5. 5: • The RST 6. 5 and RST 5. 5 both are level triggered. . i. e. Input goes to high and stay high until it recognized. • Mask able interrupt Ways to disable interrupt: 1. DI, SIM instruction 2. System or processor reset. 3. After reorganization of interrupt. • Enabled by EI instruction • The RST 6. 5 has the third priority • RST 5. 5 has the fourth priority

INTR: • Mask able interrupt. • It is disabled by, 1. DI, SIM instruction 2. System or processor reset. 3. After reorganization of interrupt. • Enabled by EI instruction • Non- vectored interrupt • After receiving INTA (active low) signal, it has to supply the address of ISR • It has lowest priority • It is a level sensitive interrupts.

Hardware Interrupt Summary

Software interrupts ØThe software interrupts are program instructions. These instructions are inserted at desired locations in a program. ØThe 8085 has eight software interrupts from RST 0 to RST 7. The vector address for these interrupts can be calculated as follows. ØInterrupt number * 8 = vector address For RST 5, 5 * 8 = 40 = 28 H Vector address for interrupt RST 5 is 0028 H ØThe Table shows the vector addresses of all interrupts.

Procedure Calls

Use of Stack

INSTRUCTION SET An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor supports is called instruction set. The instruction set consists of both machine code and mnemonics.

INSTRUCTION SET • 8085 has 246 instructions • Each instruction is represented by an 8 -bit binary value • These 8 -bits of binary value is called Op-Code or Instruction Byte

CLASSIFICATION BASED ON LENGTH 1. One-byte instructions Ø Instruction having one byte in machine code Example: Ø MOV B, C Ø MOV B, M

CLASSIFICATION BASED ON LENGTH 2. Two-byte instructions Ø Instruction having two byte in machine code

CLASSIFICATION BASED ON LENGTH 3. Three-byte instructions Ø Instruction having three byte in machine code

TIMING DIAGRAM Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states. ØInstruction Cycle: The time required to execute an instruction is called instruction cycle. ØMachine Cycle: The time required to access the memory or input/output devices is called machine cycle. ØT-State: The machine cycle and instruction cycle takes multiple clock periods. T-state is defined as one subdivision of operation performed in one clock period.

MACHINE CYCLES OF 8085 The 8085 microprocessor has 5 (Five) basic machine cycles. They are 1. 2. 3. 4. 5. Opcode fetch cycle (4 T) Memory read cycle (3 T) Memory write cycle (3 T) I/O read cycle (3 T) I/O write cycle (3 T)

MACHINE CYCLES OF 8085 Ø Each instruction of the 8085 processor consists of one to five machine cycles, i. e. , when the 8085 processor executes an instruction, it will execute some of the machine cycles in a specific order. Ø The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a machine cycle is expressed in T-states. Ø One T-state is equal to the time period of the internal clock signal of the processor. Ø The T-state starts at the falling edge of a clock.

MACHINE CYCLES OF 8085 Ø Status signals are used to specify the type of operation being performed S 1 S 0 States 0 0 HALT 0 1 WRITE 1 0 READ 1 1 FETCH

1. Op-code fetch machine cycle of 8085 ØEach instruction of the processor has one byte op-code ØThe op-codes are stored in memory. So, the processor executes the op-code fetch machine cycle to fetch the op-code from memory ØHence, every instruction starts with op-code fetch machine cycle ØThe time taken by the processor to execute the op-code fetch cycle is 4 T ØIn this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor

Opcode fetch machine cycle of 8085

2. Memory Read Cycle ØThe memory read machine cycle is executed by the processor to read a data byte from memory. ØThe processor takes 3 T states to execute this cycle. ØThe instructions which have more than one byte word size will use the machine cycle after the op-code fetch machine cycle.

2. Memory Read Cycle

3. Memory Write Cycle ØThe memory write machine cycle is executed by the processor to write a data byte in a memory location ØThe processor takes, 3 T states to execute this machine cycle

3. Memory Write Cycle

4. I/O Read Cycle ØThe I/O Read cycle is executed by the processor to read a data byte from I/O port or from the peripheral, which is I/O, mapped in the system ØThe processor takes 3 T states to execute this machine cycle ØThe IN instruction uses this machine cycle during the execution

4. I/O Read Cycle

5. I/O Write Cycle ØThe I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to a peripheral, which is I/O, mapped in the system ØThe processor takes, 3 T states to execute this machine cycle ØThe OUT instruction uses this machine cycle during the execution

5. I/O Write Cycle

Example: Timing Diagram of instruction “STA 526 AH” Recap ØThe 8085 instructions consist of one to five machine cycles. ØActually the execution of an instruction is the execution of the machine cycles of that instruction in the predefined order. ØThe timing diagram of an instruction is obtained by drawing the timing diagrams of the machine cycles of that instruction, one by one in the order of execution.

Example: Timing Diagram of instruction “STA 526 AH” ØSTA means Store Accumulator -The contents of the accumulator is stored in the specified address(526 A). ØThe op-code of the STA instruction is said to be 32 H. It is fetched from the memory 41 FFH(see fig). –Op-code Fetch Machine Cycle ØThen the lower order memory address is read(6 A). - Memory Read Machine Cycle ØRead the higher order memory address (52). - Memory Read Machine Cycle ØThe combination of both the addresses are considered and the content from accumulator is written in 526 A. - Memory Write Machine Cycle ØAssume the memory address for the instruction and let the content of accumulator is C 7 H. So, C 7 H from accumulator is now stored in 526 A.

Example Diagram of instruction “STA 526 AH”

REVIEW