KUECHIP 2 RTL Description in VHDL Version 0

-- KUE-CHIP 2 RTL Description in VHDL Version 0. 30 1997/Jul. /07 -- Copyright 1997 ASTEM RI Written by H. Kanbara library IEEE; use IEEE. std_logic_1164. all; use IEEE. std_logic_unsigned. all; use WORK. pkg_kue 2. all; entity kue_chip 2 is port(CLOCK_p : in std_logic; RESET_p : in std_logic; DBI_p : in std_logic_vector(7 downto 0); SP_p : in std_logic; SI_p : in std_logic; SS_p : in std_logic; SET_p : in std_logic; ADR_INC_p : in std_logic; ADR_DEC_p : in std_logic; OBS_SEL_p : in std_logic_vector(3 downto 0); IBUF_FLG_IN_p : in std_logic; OP_p : out std_logic; PHASE_p : out std_logic_vector(4 downto 0); AB_p : out std_logic_vector(8 downto 0); OB_p : out std_logic_vector(7 downto 0); DBO_p : out std_logic_vector(7 downto 0); MEM_OB_p : out std_logic; MEM_RE_p : out std_logic; MEM_WE_p : out std_logic; IBUF_FLG_CLR_p : out std_logic; IBUF_RE_p : out std_logic; PANEL_RE_p : out std_logic; OBUF_WE_p : out std_logic ); end kue_chip 2; 2004 9月 新大　集積回路 VHDL記述 15

RTL設計品質を高める module top(clk, i 1, i 2, o 1, o 2); input clk; input i 1, i 2; output o 1, o 2; assign w 1 = i 1 & i 2; assign w 2 = i 1 | i 2; always @(posedge clk) begin o 1 = w 1; end always @(posedge clk) begin o 2 = w 2; endmodule RTL構文チェック RT qualify RTL 後 程の制約違反を事前に回避 コードカバレッジ チェック テストベクタ Verification Navigator 10100110111 00111100101 1101 ………… RTLの機能検証抜けをなくす 2004 9月 新大　集積回路 16

フロアプランと論理合成 合成条件の生成 set_input_delay 0. 011302 -clock [get_clocks {clk 81 s}] -fall -min -add_delay [get_ports {iopctr 1 db_11}] set_input_delay 7. 537164 -clock [get_clocks {clk 81 s}] -rise -max -add_delay [get_ports {ipdrcr_21}] set_input_delay 0. 049733 -clock [get_clocks {clk 81 s}] -rise -min -add_delay [get_ports {ipdrcr_21}] 合成用ブロック入出力 タイミング制約を生成 2004 9月 新大　集積回路 20